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Logic Analyzer 的代码
poc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY POC IS
PORT(A0,RW,CLOCK,CS,RDY,RESET:IN STD_LOGIC;
DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TR,IRQ:OUT STD_LOGIC;
printer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRINTER IS
PORT(CLOCK,TR,RESET:IN STD_LOGIC;
PD:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RDY:BUFFER STD_LOGIC;
7bjq.txt
要求用VHDL语言设计7人表决器电路，了解变量和信号的区别，了解进程内部顺序语句及外部并行语句的区别。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 IS
PORT
( men: IN std_logic_vector(6 do
移位寄存器.txt
--4位移位寄存器
--DIR:控制方向,高电平向右
--CLK:时钟端,高电平触发
--CLR:同步清零端,高电平触发
--SET:同步置位端,高电平触发
--LOAD:高电平触发,保存数据
--CE:时钟控制端,高电平有效
-------------------------------------------------------------------------------
移位寄存器.txt
--4位移位寄存器
--DIR:控制方向,高电平向右
--CLK:时钟端,高电平触发
--CLR:同步清零端,高电平触发
--SET:同步置位端,高电平触发
--LOAD:高电平触发,保存数据
--CE:时钟控制端,高电平有效
-------------------------------------------------------------------------------
7bjq.txt
要求用VHDL语言设计7人表决器电路，了解变量和信号的区别，了解进程内部顺序语句及外部并行语句的区别。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 IS
PORT
( men: IN std_logic_vector(6 do
testcnt.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end entity testcnt;
architecture io of testcnt is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal st:
shizhong.vhd
Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shizhong is
port(
inclk : in std_logic;
set :in std_logic;
mode :in std_logic;
outa :out
53_counter.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
end component;
end mycntpkg;
topdesign.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
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entity Design