testcnt.vhd

来自「可预置16位计数器可预置16位计数器可预置16位计数器」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.std_logic_1164.all;

entity testcnt is
end entity testcnt;

architecture io of testcnt is
  signal clk: std_logic := '0';
  signal rst: std_logic := '1';
  signal st:  std_logic :='0';
  signal lck: std_logic := '1';
  signal dd: std_logic_vector(15 downto 0) := "0010010000011100";
  signal qq: std_logic_vector(15 downto 0) := "0000111111000000";
begin
  g1: entity WORK.counter(rtl) port map (clock=>clk, reset=>rst, set=>st, lock=>lck, pin=>dd, count=>qq);
  rst <= '0' after 10 ns;
  st <= '1' after 100 ns;
  lck <= '0' after 50 ns;
  clk <= not clk after 20 ns; 
end architecture io;