printer.vhd

用VHDL语言讲述输出控制器（POC）的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRINTER IS
       PORT(CLOCK,TR,RESET:IN STD_LOGIC;
            PD:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
            RDY:BUFFER STD_LOGIC;
            P_DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END PRINTER;

ARCHITECTURE BEHAVE OF PRINTER IS
SIGNAL COUNT:integer range 1 to 7;
BEGIN
PROCESS(CLOCK,RESET)
BEGIN
IF(RESET='0')THEN P_DATA<="00000000";
   ELSIF RISING_EDGE(CLOCK) THEN
     IF RISING_EDGE(TR) THEN RDY<='0';
     END IF;
--END IF;
--END PROCESS;

--PROCESS(CLOCK)
--BEGIN
     IF(RDY='1') THEN COUNT<=1;
     ELSIF(COUNT<7) THEN P_DATA<=PD;COUNT<=COUNT+1;
     END IF;
END IF;
END PROCESS;
END BEHAVE;