topdesign.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
------------------------------------------------------
entity DesignTop is
    Port ( clk,ps2_clk,ps2_data  : in  STD_LOGIC;				
           ctrlled : inout  STD_LOGIC_vector(3 downto 0 ) ;
			  SW7,SW6,SW5,SW4,SW3,SW2,SW1,SW0 : in STD_LOGIC;
			  button,Rx : in STD_LOGIC;
				RGB	: out STD_LOGIC_vector(2 downto 0 ) ;
				HS,VS,Tx: out STD_LOGIC;
			  segtoled : out  STD_LOGIC_VECTOR (7 downto 0));
end DesignTop;
-----------------------------------------------------
architecture Behavioral of DesignTop is	
-----------------------------------------------------
	component divclk_3
		 Port ( clk0 : in  STD_LOGIC;
           clk2,clk3 : out STD_LOGIC);
	end component;	
-----------------------------------------	
	component debounce 
		 port(clk,button : in std_logic;
				cntpulse : out std_logic );
	end component;	
---------------------------------------------------------
	component Counthand is
    Port ( SW1,SW0,SW2 : in  STD_LOGIC;
				cntpulse  :in  std_logic;
    		  BCD0,BCD1,BCD2,BCD3:out std_logic_VECTOR (3 downto 0));
	end component;	
------------------------------------------------------------	
	component TopKbWatch 
    Port ( clk,ps2_data,ps2_clk : in  STD_LOGIC;
         SW7,SW6,SW5,SW4: in  STD_LOGIC;
			ledin0,ledin1,ledin2,ledin3,ledin4,ledin5 : out  STD_LOGIC_VECTOR (3 downto 0));
	end component;	
----------------------------------------------------------------	
	component Countsp is
    Port ( clk,SW1,SW0,SW2 : in  std_logic;
    		  BCD0,BCD1,BCD2,BCD3:out std_logic_VECTOR (3 downto 0));
	end component;		
----------------------------------------------------------------
	component displed 
   Port ( ps2clk,ps2data,clk50: in  STD_LOGIC;
			 ledout0,ledout1,ledout2,ledout3,ledout4,ledout5:in STD_LOGIC_vector(7 downto 0);
			 ledoutsp0,ledoutsp1,ledoutsp2,ledoutsp3:in STD_LOGIC_vector(7 downto 0);
			 ledtay0,ledtay1,ledtay2,ledtay3:in STD_LOGIC_vector(7 downto 0); 
			 AN: inout  STD_LOGIC_vector(3 downto 0);
			 SW0,SW1,SW2,SW3: in STD_LOGIC;		
			 HS : out STD_LOGIC;
			 VS : out STD_LOGIC;
			 RGB_out : out std_logic_vector (2 downto 0);
			 Tx:out STD_LOGIC;			
			 Rx:in STD_LOGIC;
			 display:out STD_LOGIC_vector(7 downto 0));
	end component;	
------------------------------------------------------------	
	component decoderbcd
		Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);
           segs : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;	
-----------------------------------------------------------------
	component decoderbcddot
		Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);
           segs : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;	
------------------------------------------------------	
	signal clk2,clk3,cntpulse: std_logic;
	signal leds0,leds1,leds2,leds3,leds4,leds5: STD_LOGIC_VECTOR (3 downto 0);
	signal segleds0,segleds1,segleds2,segleds3,segleds4,segleds5: STD_LOGIC_VECTOR (7 downto 0);
	signal SP0,SP1,SP2,SP3: STD_LOGIC_VECTOR (3 downto 0);
	signal segsp0,segsp1,segsp2,segsp3: STD_LOGIC_VECTOR (7 downto 0);
	signal hSP0,hSP1,hSP2,hSP3: STD_LOGIC_VECTOR (3 downto 0);
	signal hsegsp0,hsegsp1,hsegsp2,hsegsp3: STD_LOGIC_VECTOR (7 downto 0);
begin
U0:divclk_3 port map(clk,clk2,clk3);
U01:debounce port map (clk3,button,cntpulse);
U1:Counthand port map(SW1,SW0,SW2,cntpulse,hSP0,hSP1,hSP2,hSP3);
U2:TopKbWatch port map(clk,ps2_data,ps2_clk,SW7,SW6,SW5,
			SW4,leds0,leds1,leds2,leds3,leds4,leds5);
U3:Countsp port map(clk2,SW1,SW0,SW2,SP0,SP1,SP2,SP3);
--------------------------------------------------------------------
U4: displed port map(ps2_clk,ps2_data,clk,segleds0,segleds1,segleds2,
		segleds3,segleds4,segleds5,segsp0,segsp1,segsp2,
		segsp3,hsegsp0,hsegsp1,hsegsp2,hsegsp3,
		ctrlled,SW0,SW1,SW2,SW3,HS,VS,RGB,Tx,Rx,segtoled );
-----------------------------------------------------------------		
U10:decoderbcd port map(SP0,segsp0);
U11:decoderbcd port map(SP1,segsp1);
U12:decoderbcd port map(SP2,segsp2);
U13:decoderbcd port map(SP3,segsp3);	

S3:decoderbcd  port map(leds0,segleds0);
S4:decoderbcd  port map(leds1,segleds1);
S5:decoderbcddot port map(leds2,segleds2);
S6:decoderbcd  port map(leds3,segleds3);
S7:decoderbcddot port map(leds4,segleds4);
S8:decoderbcd  port map(leds5,segleds5);

U30:decoderbcd port map(hSP0,hsegsp0);
U31:decoderbcd port map(hSP1,hsegsp1);
U32:decoderbcd port map(hSP2,hsegsp2);
U33:decoderbcd port map(hSP3,hsegsp3);

end Behavioral;