vga.vhd

来自「many application on kit SP-3: VGA, digit」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL ;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Vga is
Port ( CLK : in STD_LOGIC;
			RGB_in : in std_logic_vector (2 downto 0);
			HS : out STD_LOGIC;
			VS : out STD_LOGIC;
			CntH : out std_logic_vector (9 downto 0);
			CntV : out std_logic_vector (9 downto 0);
			RGB_out : out std_logic_vector (2 downto 0));
end Vga;

architecture Behavioral of Vga is

component Vga_interface is
Port ( CLK : in STD_LOGIC;
			HS : out STD_LOGIC;
			VS : out STD_LOGIC;
			X : out std_logic_vector (9 downto 0);
			Y : out std_logic_vector (9 downto 0);
			Blank : out std_logic);
end component;

signal Temp_X : std_logic_vector (9 downto 0);
signal Temp_Y : std_logic_vector (9 downto 0);
signal Blank : std_logic;

begin

U410 : Vga_interface port map (CLK, HS, VS, Temp_X,Temp_Y,Blank);
	process (clk)
	begin
		if (Blank = '1') then
			RGB_out <= RGB_in;
		else
			RGB_out <= "000";
		end if ;
	CntH <= Temp_X;	
	CntV <= Temp_Y;
	end process;
end Behavioral;