7bjq.txt

包含VHDL语言设计7人表决器电路和系检测器列

要求用VHDL语言设计7人表决器电路，了解变量和信号的区别，了解进程内部顺序语句及外部并行语句的区别。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY vote7 IS
    PORT
    (    men: IN    std_logic_vector(6 downto 0);
        pass,stop    : buffer std_logic
           );
    
END vote7;

ARCHITECTURE behave OF vote7 IS
BEGIN
 stop<=not pass;
    PROCESS (men)
         variable temp:std_logic_vector(2 downto 0);
    BEGIN
             temp:="000";
        for i in 0 to 6 loop
                if(men(i)='1') then
                   temp:=temp+1;
                else
                   temp:=temp+0;
                end if;
              end loop;    
            pass<=temp(2);
            stop<=not(pass);
    END PROCESS;
 END behave;