移位寄存器.txt

包含VHDL语言设计7人表决器电路和系检测器列

--4位移位寄存器
--DIR:控制方向,高电平向右
--CLK:时钟端,高电平触发
--CLR:同步清零端,高电平触发
--SET:同步置位端,高电平触发
--LOAD:高电平触发,保存数据
--CE:时钟控制端,高电平有效
---------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity shft_reg is
port (
DIR : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
SI : in std_logic;
DATA : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(3 downto 0)
);
end entity;



architecture shft_reg_arch of shft_reg is
signal TEMP_data_out : std_logic_vector(3 downto 0);
begin

process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
 if CLR = '1' then
  TEMP_data_out <= "0000";
      elsif SET = '1' then
       TEMP_data_out <= "1111";
      elsif LOAD = '1' then
       TEMP_data_out <= DATA;
      else
       if DIR = '1' then
                TEMP_data_out <= SI & TEMP_data_out(3 downto 1);
                else
          TEMP_data_out <= TEMP_data_out(2 downto 0) & SI;
       end if;
      end if;
  end if;
end if;
end process;

data_out <= TEMP_data_out;

end architecture;