poc.vhd

用VHDL语言讲述输出控制器（POC）的设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY POC IS
       PORT(A0,RW,CLOCK,CS,RDY,RESET:IN STD_LOGIC;
            DATA:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
            TR,IRQ:OUT STD_LOGIC;
            PD:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END POC;

ARCHITECTURE BEHAVE OF POC IS
SIGNAL SR0,SR7:STD_LOGIC;
SIGNAL BR:STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE STATE_VALUE IS (S0,S1,S2,S3);
SIGNAL POCSTATE:STATE_VALUE;

BEGIN
PROCESS(CLOCK,RESET)
BEGIN
     IF (RESET='0') THEN POCSTATE<=S0;
     ELSIF RISING_EDGE(CLOCK) THEN
        IF (SR7='0') THEN POCSTATE<=S1;---BUSY
        ELSIF (SR0='0') THEN POCSTATE<=S2;---REDY,CAN TRANSTORT DATA
           ELSE POCSTATE<=S3;--interrupt
        END IF;
     END IF;
END PROCESS;

PROCESS(RDY)
BEGIN
---IF RISING_EDGE(CLOCK) THEN        
   CASE POCSTATE IS
     WHEN S0=>
          BR<="00000000";SR0<='0';SR7<='0';
     WHEN S1=>
          PD<=BR;SR7<='0';
          IF(RDY='1')  THEN TR<='1'; END IF;
          IF(RDY='0') THEN TR<='0'; END IF;
          IF(RISING_EDGE(RDY)) THEN SR7<='1';END IF; 
     WHEN S2=>
          BR<=DATA;SR7<='0';
     WHEN S3=>
          IRQ<='1';
   END CASE;
--END IF;
END PROCESS;
END BEHAVE;