shizhong.vhd

多功能数字时钟设计方案及电路图

Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity shizhong is
	port(
		 inclk : in std_logic;
		 set   :in std_logic;
		 mode  :in std_logic;
		 outa  :out std_logic_vector(0 to 6);
		 outb  :out std_logic_vector(0 to 6);
		 outc  :out std_logic_vector(0 to 6);
		 bitout:out std_logic_vector(2 downto 0)
		);
end shizhong;
architecture behav of shizhong is

component fp
	port(inclk :in std_logic;
		 fpa  :out std_logic;
		 fpb  :out std_logic;
		 fpc  :out std_logic
		);
end component;

component adjuster
	port(
		  inclk: in std_logic;
		  set  : in std_logic;
		  mode : in std_logic;
		  En   : in std_logic;
		  flag : out std_logic;
		  fpb  :out std_logic;
		  clk  :out std_logic;
		  s_count:in std_logic;
		  m_count:in std_logic;
		  s_en   :out std_logic;
		  m_en   :out std_logic;
		  h_en   :out std_logic;
		  mm_en  :out std_logic;
		  conver :out std_logic
		 );
end component;

component counter60
	port( En   : in std_logic;
		  inclk: in std_logic;
		  fpb  : in std_logic;
		  count: out std_logic;
		  Low  : out std_logic_vector(3 downto 0);
		  High : out std_logic_vector(3 downto 0)
		);
end component;

component counter24 
  port(inclk:in std_logic;
	   fpb  :in std_logic;
	   En   :in std_logic;
	   conver:in std_logic;
       High :out std_logic_vector(3 downto 0);
	   Low  :out std_logic_vector(3 downto 0));
end component;

component counter100
	port( En   : in std_logic;
		  inclk: in std_logic;
		  fpc  : in std_logic;
		  Low  : out std_logic_vector(3 downto 0);
		  High : out std_logic_vector(3 downto 0)
		);
end component;


	constant Vcc :std_logic :='1';
	signal SL,SH,ML,MH,HL,HH,MML,MMH:std_logic_vector(3 downto 0);
	signal bit    :std_logic_vector(2 downto 0);
	signal st     :std_logic_vector(2 downto 0);
	signal fpa,fpb,fpc,clk:std_logic;
	signal s_en,m_en,h_en,mm_en:std_logic;
	signal s_count,m_count:std_logic;
	signal Vcc_con:std_logic;
	signal conver12:std_logic;
	signal flag    :std_logic;
	signal mseg   :std_logic_vector(3 downto 0);
	signal blink  :std_logic_vector(6 downto 0) :="1111111";
	signal outa1  :std_logic_vector(6 downto 0);
	--signal cnt  :std_logic_vector(5 downto 0);
begin
P1:fp
	port map( 	fpa=>fpa,
				fpb=>fpb,
				fpc=>fpc,
				inclk=>inclk
			);
P2:adjuster
 	port map(
				En=>Vcc_con,
				inclk=>fpb,
				set=>set,
				flag=>flag,
				mode=>mode,
				clk=>clk,
				s_en=>s_en,
				m_en=>m_en,
				h_en=>h_en,
				mm_en=>mm_en,
				s_count=>s_count,
				m_count=>m_count,
				conver=>conver12
			);

Vcc_con<=Vcc;
P3:counter60
	port map(
				Low=>SL,
				High=>SH,
				En=>s_en,
				inclk=>inclk,
				fpb=>clk,
				count=>s_count
			);
P4:counter60
	port map(
				Low=>ML,
				High=>MH,
				En=>m_en,
				inclk=>inclk,
				fpb=>clk,
				count=>m_count
			);
P5:counter24
	port map(
				Low=>HL,
				High=>HH,
				En=>h_en,
				inclk=>inclk,
				fpb=>clk,
				conver=>conver12
			);
P6:counter100
	port map(
				Low=>MML,
				High=>MMH,
				En=>mm_en,
				inclk=>inclk,
				fpc=>fpc
			);


process(fpa,inclk)
					begin
						if(fpa'event and fpa='1')then
							st<=st+1;
						end if;
						case st is
						  when "000"=> bit<="000";mseg<=SL;
						  when "001"=> bit<="001";mseg<=SH;
						  when "010"=> bit<="010";mseg<="1100";
						  when "011"=> bit<="011";mseg<=ML;
						  when "100"=> bit<="100";mseg<=MH;
						  when "101"=> bit<="101";mseg<="1101";
						  when "110"=> bit<="110";mseg<=HL;
						  when "111"=> bit<="111";mseg<=HH;
						  when others=>NULL;
						end case;
				end process;
				bitout<=bit;
					process(fpb)
						begin
							if fpb'event and fpb='1' then
								if flag='0' then
									blink<=not blink;
							    else 
									blink<="1111111";
							    end if;
							end if;
					end process;
				 with mseg select
					 outa1<= "0110000"when"0001",
		 					"1101101"when"0010",
		 					"1111001"when"0011",
		 					"0110011"when"0100",
		 					"1011011"when"0101",
		 					"1011111"when"0110",
		 					"1110000"when"0111",
		 					"1111111"when"1000",
		 					"1111011"when"1001",
		 					"1110111"when"1010",
		 					"0011111"when"1011",
		 					"0000001"when"1100",
		 					"0000001"when"1101",                                                                                                                                                                                                                                             
		 					"1001111"when"1110",
		 					"1000111"when"1111",
		 					"1111110"when others;
					process(inclk,flag,bit)
						begin
						  if flag='0' then
							 if s_en='1' then
								if bit="000" or bit="001" then
									outa<=outa1 and blink;
									else outa<=outa1;
								end if;
							 else
							  if m_en='1' then
								   if bit="011" or bit="100" then
										outa<=outa1 and blink;
									else outa<=outa1;
								   end if;
							   else
									if bit="110" or bit="111" then
										outa<=outa1 and blink;
									else outa<=outa1;
								    end if;
							  end if;
							 end if;
						   else
							  outa<=outa1;
						   end if;
					end process;
				 with MML select
					 outc<= "0110000"when"0001",
		 					"1101101"when"0010",
		 					"1111001"when"0011",
		 					"0110011"when"0100",
		 					"1011011"when"0101",
		 					"1011111"when"0110",
		 					"1110000"when"0111",
		 					"1111111"when"1000",
		 					"1111011"when"1001",
		 					"1110111"when"1010",
		 					"0011111"when"1011",
		 					"0000001"when"1100",
		 					"0000001"when"1101",                                                                                                                                                                                                                                             
		 					"1001111"when"1110",
		 					"1000111"when"1111",
		 					"1111110"when others;
				 with MMH select
					 outb<= "0110000"when"0001",
		 					"1101101"when"0010",
		 					"1111001"when"0011",
		 					"0110011"when"0100",
		 					"1011011"when"0101",
		 					"1011111"when"0110",
		 					"1110000"when"0111",
		 					"1111111"when"1000",
		 					"1111011"when"1001",
		 					"1110111"when"1010",
		 					"0011111"when"1011",
		 					"0000001"when"1100",
		 					"0000001"when"1101",                                                                                                                                                                                                                                             
		 					"1001111"when"1110",
		 					"1000111"when"1111",
		 					"1111110"when others;


end behav;