counter24.vhd

来自「多功能数字时钟设计方案及电路图」· VHDL 代码 · 共 83 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
port(inclk:in std_logic;
	 fpb  :in std_logic;
	 En   :in std_logic;
	 conver:in std_logic;
     High :out std_logic_vector(3 downto 0);
	 Low  :out std_logic_vector(3 downto 0));
end counter24;
architecture arch_counter24 of counter24 is
signal sa:std_logic_vector(3 downto 0);
signal sb:std_logic_vector(3 downto 0);
begin
process(inclk,fpb)
begin 
	if (rising_edge(fpb))then
	 if En='1' then
	  if(sa=3 and sb=2) then
	  	sa<="0000";
		sb<="0000";
	  else
		if sa=9 then
		   sa<="0000";
		   sb<=sb+1;
		else
		   sa<=sa+1;
		end if ;
	  end if;
	 end if;
	end if;
if conver='1' then
  Low<=sa;
  High<=sb;
elsif conver='0' then
	if sb=1 then
	  case sa is
		when "0000"=> Low<="0000";
				      High<="0001";
		when "0001"=> Low<="0001";
				      High<="0001";		
		when "0010"=> Low<="0010";
				      High<="0001";		
		when "0011"=> Low<="0001";
				      High<="0000";				
		when "0100"=> Low<="0010";
				 	  High<="0000";		
		when "0101"=> Low<="0011";
				 	  High<="0000";		
		when "0110"=> Low<="0100";
				 	  High<="0000";		
		when "0111"=> Low<="0101";
				      High<="0000";		
		when "1000"=> Low<="0110";
				 	  High<="0000";
		when "1001"=> Low<="0111";
				 	  High<="0000";	
		when others=> Low<="0111";
				 	  High<="0000";
		end case;
	else if sb=2 then
		case sa is
		when "0000"=> Low<="1000";
				      High<="0000";		
		when "0001"=> Low<="1001";
				 High<="0000";		
		when "0010"=> Low<="0000";
				 High<="0001";
		when "0011"=> Low<="0001";
				 	  High<="0001";
		when others=> Low<="0001";
				 High<="0001";
		end case;
	 	else
		  High<=sb;
		  Low<=sa;
		end if;
	end if;
	end if;				
end process;
end arch_counter24;