counter100.vhd

来自「多功能数字时钟设计方案及电路图」· VHDL 代码 · 共 40 行

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
	port( En   : in std_logic;
		  inclk: in std_logic;
		  fpc  : in std_logic;
		  count: out std_logic;
		  Low  : out std_logic_vector(3 downto 0);
		  High : out std_logic_vector(3 downto 0)
		);
end counter100;
architecture counter100_arch of counter100 is
 	signal ma,mb :std_logic_vector(3 downto 0);
	 begin
	   process(inclk,fpc,En)
			begin
			   if fpc'event and fpc='1' then
				 if En='1' then
					if ma=9 then
						ma<="0000";
						if mb=9 then
							mb<="0000";
							else
								mb<=mb+1;
						    end if;
					else
						ma<=ma+1;
					end if;
				  else
					ma<="0000";
					mb<="0000";
				end if;
			   end if;
               	Low<=ma;
				High<=mb;
		end process;
end counter100_arch;