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找到约 10,000 项符合
Logic Analyzer 的代码
myclock.vhd
--顶层文件
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity myclock is
Port(clk,reset,set:in std_logic;
en:in std_logic_ve
day1.vhd
Library ieee; --每月天数模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity day1 is
Port(clkday,set,reset:in std_logic;
d1,d
second1.vhd
Library ieee; --秒钟模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity second1 is
Port(clk,set,reset:in std_logic;
xianshi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
port (clk_12M :in std_logic; --系统时钟
din:in std_logic_vector(23 downto
test.vhd
-- Project: VHDL to Verilog RTL translation
-- Revision: 1.0
-- Date of last Revision: February 27 2001
-- Designer: Vincenzo Liguori
-- vhd2vl test file
-- This VHDL fil
LIBRARY IEEE;
USE IEEE.
my_83.vhd
-- MAX+plus II VHDL
-- Clearable my_83
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY my_83 IS
PORT
(
d : IN STD_LOGIC_VECTOR(0 to 7);
Ein : IN STD_LOGIC;
Gsn,Eon
q7230.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Q7230 is
generic (Byte : integer :=8);
port(
CLK,OE,reset : in std_logic;
Din : in s
9999计数器模块 四输出.txt
——9999计数器模块 四输出
设计要求频率计为四段显示，故计数器采用0~~9999计数，可以很好的利用数码管，以及增加频率计的精确度。模块内包含俩个进程，一为计数进程，二为时基信号控制计数模块数据输出进程。
LIBRARY IEEE;
USE IEEE.STD_<mark>LOGIC</mark>_1164.ALL;
USE IEEE.STD_<mark>LOGIC</mark>_ARITH.ALL;
USE IEEE.STD_ ...
scandisp.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
entity ScanDisp is
port(
clk1KHZ,reset: in std_logic;
outdis: in std_logic_vect
scandisp.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
entity ScanDisp is
port(
clk,reset: in std_logic;
outdis: in std_logic_vector(1