xianshi.vhd

数字秒表的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xianshi is
  port (clk_12M :in std_logic;                      --系统时钟
        din:in std_logic_vector(23 downto 0);
        dout:out std_logic_vector(3 downto 0);
        w1 :out std_logic_vector(2 downto 0));    --数码管位选信号
end ;
architecture behav of xianshi is
signal qq : integer range 0 to 176944;                   --动态扫描分频系数
begin
process(clk_12M)            --此进程完成数据的动态显示
begin
  if clk_12M'event and clk_12M='1' then 
        if qq<22118 then qq<=qq+1;dout<=din(3 downto 0); w1<="000"; 
	    	       
           elsif qq<44236 then qq<=qq+1;dout<=din(7 downto 4); w1<="001";
	      
             elsif qq<66354 then qq<=qq+1;dout<=din(11 downto 8); w1<="010";
	      
	            elsif qq<88472 then qq<=qq+1;dout<=din(15 downto 12); w1<="011"; 
          
                  elsif qq<110590 then qq<=qq+1;dout<=din(19 downto 16); w1<="100"; 
          
                    elsif qq<132708 then qq<=qq+1;dout<=din(23 downto 20); w1<="101"; 
        
         else  qq<=0;
         end if;
  end if;
end process;
end behav;