myclock.vhd

能自动记时

--顶层文件
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity myclock is
   Port(clk,reset,set:in std_logic;
        en:in std_logic_vector(1 downto 0); 
        a0,a1,a2,a3,a4,a5,a6:in std_logic_vector(3 downto 0); 
        b0,b1,b2,b3,b4,b5,b6:buffer std_logic_vector(3 downto 0));
End;
          
Architecture one of myclock is
   Component second1                                        
      Port(clk,set,reset:in std_logic;
      s1,s0:in std_logic_vector(3 downto 0);         --置数端（秒） 
      sec1,sec0:buffer std_logic_vector(3 downto 0);  --秒输出端     
      ensec:out std_logic);              --秒计时器的进位，用来驱动分计时器
   End Component;
   Component minute1                                        
       Port(clkm,set,reset:in std_logic;
            m1,m0:in std_logic_vector(3 downto 0);         --置数端（分） 
            min1,min0:buffer std_logic_vector(3 downto 0);  --分输出端     
            enmin:out std_logic);              --分计数器  
   End Component;
   Component hour1                                          
           Port(clkh,set,reset:in std_logic;
      h1,h0:in std_logic_vector(3 downto 0);
      hour1,hour0:buffer std_logic_vector(3 downto 0);
      enday:out std_logic);  
   End Component;
   Component week1                                           
      Port(clkday,set,reset:in std_logic;
           w1:in std_logic_vector(3 downto 0);        
           week:buffer std_logic_vector(3 downto 0)); 
   End Component;
   Component day1          
      Port(clkday,set,reset:in std_logic;
      d1,d0:in std_logic_vector(3 downto 0);              
      da1,da0:buffer std_logic_vector(3 downto 0);  
      enmon:out std_logic); 
   End Component;
 Component month1          
      Port(clkd,set,reset:in std_logic;
      mo1,mo0:in std_logic_vector(3 downto 0);
      month1,month0:buffer std_logic_vector(3 downto 0);
      enyear:out std_logic);  
   End Component;
 Component year1          
      Port(clky,set,reset:in std_logic;
      y1,y0:in std_logic_vector(3 downto 0);
      year1,year0:buffer std_logic_vector(3 downto 0));  
 End Component;
 signal enm,enh,enda,enmo,eny:std_logic;
 signal c0,c1 ,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12:  STD_LOGIC_vector(3 downto 0);
 begin
u1:second1 port map(reset=>reset,set=>set,s1=>c1,s0=>c0,sec1=>d1,sec0=>d0,clk=>clk, ensec=>enm);
u2:minute1 port map(reset=>reset,set=>set,m1=>c3,m0=>c2,min1=>d3,min0=>d2,clkm=>enm,enmin=>enh);
u3:hour1 port map(reset=>reset,set=>set,h1=>c5,h0=>c4,hour1=>d5,hour0=>d4,clkh=>enh, enday=>enda);
u4:week1 port map(reset=>reset,set=>set,w1=>c6,week=>d6,clkday=>enda);
u5:day1 port map(reset=>reset,set=>set,d1=>c8,d0=>c7,da1=>d8, da0=>d7,clkday=>enda,enmon=>enmo);
u6:month1 port map(reset=>reset,set=>set,mo1=>c10,mo0=>c9,month1=>d10, month0=>d9,clkd=>enmo,enyear=>eny);
u7:year1 port map(reset=>reset,set=>set,y1=>c12,y0=>c11,year1=>d12, year0=>d11,clky=>eny);
process(en)
begin
case en is       
when "00"=>b0<=d0;b1<=d1;b2<=d2;b3<=d3;b4<=d4;b5<=d5;
when "01"=>b0<=d6;b1<=d7;b2<=d8;b3<=d9;b4<=d10;b5<=d11;b6<=d12;
when others=>b0<=d0;b1<=d1;b2<=d2;b3<=d3;b4<=d4;b5<=d5;
end case;
end process;
end;