day1.vhd

能自动记时

Library ieee;       --每月天数模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity day1 is
 Port(clkday,set,reset:in std_logic;
                 d1,d0:in std_logic_vector(3 downto 0);    --输入预置天数             
               da1,da0:buffer std_logic_vector(3 downto 0);  --输出天数显示
                 enmon:out std_logic);             --天数满31，进位月份加1
End day1;
Architecture a of day1 is
Begin
Process(clkday,reset,set,d1,d0)
  variable  cq1,cq0: STD_LOGIC_vector( 3 downto 0);
Begin
  if reset='1' then cq1:="0000"; cq0:="0001"; 
    Elsif clkday'event and clkday='1' then
      if ( cq1="0011" and cq0="0001" )then cq1:="0000"; cq0:="0000"; enmon<='1';  --天数满31，进位月份加1
      else enmon<='0';     
      end if;cq0:=cq0+1; 
      if cq0="1010" then cq0:="0000";cq1:=cq1+1; --天数低位满10，进位高位加1
      end if;
  end if;
  da1<=cq1;da0<=cq0;
End process;
End;