my_83.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II VHDL 
-- Clearable my_83

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_83 IS
    PORT
	(
		d		: IN	STD_LOGIC_VECTOR(0 to 7);
		Ein		: IN	STD_LOGIC;
        Gsn,Eon		: out	STD_LOGIC;
		y	: OUT 	STD_LOGIC_VECTOR(2 downto 0));		
END my_83;

ARCHITECTURE rtl OF my_83 IS
BEGIN  
PROCESS(d,Ein)
BEGIN
 if(Ein='1')then y<="111";Gsn<='1';Eon<='1';
 else
if(d="11111111")then y<="111";Gsn<='1';Eon<='0';
elsif(d(7)='0')then y<="000";Gsn<='0';Eon<='1';
elsif(d(6)='0')then y<="001";Gsn<='0';Eon<='1';
elsif(d(5)='0')then y<="010";Gsn<='0';Eon<='1';
elsif(d(4)='0')then y<="011";Gsn<='0';Eon<='1';
elsif(d(3)='0')then y<="100";Gsn<='0';Eon<='1';
elsif(d(2)='0')then y<="101";Gsn<='0';Eon<='1';
elsif(d(1)='0')then y<="110";Gsn<='0';Eon<='1';
elsif(d(0)='0')then y<="111";Gsn<='0';Eon<='1';
end if;
end if;
 END PROCESS;
END rtl;