scandisp.vhd

ＶＨＤＬ源程序

library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity ScanDisp is
  port(
	clk,reset:	in std_logic;
	outdis:	in std_logic_vector(15 downto 0);
	one:	out std_logic_vector(3 downto 0);
	sl:	 inout std_logic_vector(2 downto 0));
  end ScanDisp;

  ARCHITECTURE arch OF ScanDisp IS
  BEGIN

	scan:PROCESS(clk,reset)
	BEGIN
	  if(reset = '0') then
		sl <= "111";
	  elsif(clk'event and clk = '1') then
		if(sl > 4) then
		   sl <= sl - '1';
		else
		   sl <= "111";
		end if;
	  end if;
	END PROCESS scan;

	WITH sl SELECT
	  one <= outdis(3 downto 0)   WHEN "111",
		 	 outdis(7 downto 4)   WHEN "110",
		 	 outdis(11 downto 8)  WHEN "101",
		 	 outdis(15 downto 12) WHEN OTHERS;

  END arch;