q7230.vhd

PLD-N分频程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Q7230 is 
 generic (Byte : integer :=8);
   port(
         CLK,OE,reset : in std_logic;
         Din    : in std_logic_vector(Byte-1 downto 0);
         CP     : out std_logic
       );
end Q7230;
----**********************************************------
architecture a of Q7230 is

component MAX_256_Count Port
     (
        clk : in std_logic;
        reset : in std_logic;
        OE    : in std_logic;
        CP     : out std_logic;
       -- CpTemp: in std_logic;
        count : buffer std_logic_vector(7 downto 0)
      );
end component;
        
signal  count :  std_logic_vector(Byte-1 downto 0);
--signal  CpTemp: std_logic;

begin 
 
U1 : MAX_256_Count
 port map(
           CLK=>CLK,
           reset  =>reset,
           OE   =>OE,
           CP=>CP,
           count=>count
          );
  
end a;