max_256_count.vhd

来自「PLD-N分频程序」· VHDL 代码 · 共 32 行

library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity MAX_256_Count is
--generic (Byte : integer :=8);
   port(
         CLK,OE,reset : in std_logic;
         CP     : out std_logic;
         CpTemp: buffer std_logic;
         count : buffer std_logic_vector(7 downto 0)
       );
end MAX_256_Count;

architecture a of MAX_256_Count is

 begin
  process (CLK)
  begin
   if reset='0' then
     count<="00000000";--(others=>'0');
     CP<='0';
    elsif clk='1' and clk'event then
     count<=count+1;
    if count="00000011"then
       CpTemp<=not CpTemp;
       CP<=CpTemp;
    end if;
    end if;
  end process;
end a;