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Logic Analyzer 的代码
serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (
iface.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
leon.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
dma.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
testmod.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
leonlib.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
tb_msp.vhd
-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program
ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS
dds.vhd
--DDS.VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(M:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
CLK:IN
sum.vhd
--SUM.VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM IS
PORT(K:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
RESET:IN