📄 iface.vhd
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-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: iface
-- File: iface.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Package with type declarations for module interconnections
------------------------------------------------------------------------------
-- Version control:
-- 17-12-1997: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
package iface is
-- interface data types
-- register file inputs
type rf_in_type is record
rd1addr : std_logic_vector(RABITS-1 downto 0); -- read address 1
rd2addr : std_logic_vector(RABITS-1 downto 0); -- read address 2
wraddr : std_logic_vector(RABITS-1 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
wren : std_logic; -- write enable
end record;
-- instruction cache diagnostic access inputs
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_logic;
read : std_logic;
tag : std_logic;
flush : std_logic;
end record;
-- data cache controller inputs
type dcache_in_type is record
asi : std_logic_vector(7 downto 0); -- ASI for load/store
maddress : std_logic_vector(31 downto 0); -- memory stage address
eaddress : std_logic_vector(31 downto 0); -- execute stage address
size : std_logic_vector(1 downto 0);
signed : std_logic;
enaddr : std_logic;
nullify : std_logic;
lock : std_logic;
read : std_logic;
write : std_logic;
flush : std_logic;
end record;
-- data cache controller outputs
type dcache_out_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
mexc : std_logic; -- memory exception
wexc : std_logic; -- write exception
hold : std_logic;
mds : std_logic;
icdiag : icdiag_in_type;
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto 0); -- raw address (npc)
fpc : std_logic_vector(31 downto 0); -- latched address (pc)
branch : std_logic; -- Instruction branch
nullify : std_logic; -- instruction nullify
su : std_logic; -- super-user
flush : std_logic; -- flush icache
end record;
type icache_out_type is record
data : std_logic_vector(31 downto 0);
exception : std_logic;
hold : std_logic;
flush : std_logic; -- flush in progress
diagrdy : std_logic; -- diagnostic access ready
diagdata : std_logic_vector(31 downto 0); -- diagnostic data
mds : std_logic; -- memory data strobe
end record;
type agen_out_type is record
rpc : std_logic_vector(29 downto 0); -- unlatched PC (npc)
fpc : std_logic_vector(29 downto 0); -- fetch PC
epc : std_logic_vector(29 downto 0); -- execute PC
mpc : std_logic_vector(29 downto 0); -- memory PC
wpc : std_logic_vector(29 downto 0); -- write PC
branch : std_logic; -- Instruction branch
end record;
type rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
cb1 : std_logic_vector(6 downto 0); -- read checkbits 1
cb2 : std_logic_vector(6 downto 0); -- read checkbits 2
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_logic; -- burst request
req : std_logic; -- memory cycle request
su : std_logic; -- supervisor address space
tparerr : std_logic;
dparerr : std_logic;
flush : std_logic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
mexc : std_logic; -- memory exception
burst : std_logic; -- memory burst enable
ics : std_logic_vector(1 downto 0); -- icache state (from CCR)
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
tparerr : std_logic;
dparerr : std_logic;
flush : std_logic; -- flush in progress
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
mexc : std_logic; -- memory exception
dcs : std_logic_vector(1 downto 0);
end record;
type memory_dma_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0);
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
end record;
type memory_dma_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
mexc : std_logic; -- memory exception
end record;
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
checkbits : std_logic_vector(6 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
checkbits : std_logic_vector(6 downto 0);
ramsn : std_logic_vector(3 downto 0);
ramoen : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
type pbus_in_type is record
address : std_logic_vector(5 downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
read : std_logic;
pioh : std_logic_vector(15 downto 0);
end record;
type pbus_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type peri_in_type is record
intack : std_logic;
iv : std_logic_vector(3 downto 0);
piol : std_logic_vector(15 downto 0);
cerror : std_logic; -- EDAC correctable error
end record;
type peri_out_type is record
irl : std_logic_vector(3 downto 0);
piol : std_logic_vector(15 downto 0);
piodir : std_logic_vector(15 downto 0);
romwidth : std_logic_vector(1 downto 0);
romedac : std_logic;
wdog : std_logic;
end record;
type pio_in_type is record
piol : std_logic_vector(15 downto 0);
end record;
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(15 downto 0);
piodir : std_logic_vector(15 downto 0);
romwidth : std_logic_vector(1 downto 0);
romedac : std_logic;
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
end record;
type mctrl_in_type is record
romwidth : std_logic_vector(1 downto 0);
romedac : std_logic;
end record;
type mctrl_out_type is record
cerror : std_logic; -- EDAC correctable error
end record;
type io_in_type is record
piol : std_logic_vector(15 downto 0);
end record;
type io_out_type is record
piol : std_logic_vector(15 downto 0);
piodir : std_logic_vector(15 downto 0);
wdog : std_logic;
end record;
type sys_in_type is record
irl : std_logic_vector(3 downto 0);
end record;
type sys_out_type is record
error : std_logic;
intack : std_logic;
irqvec : std_logic_vector(3 downto 0);
end record;
type itram_in_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE - 1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
parity : std_logic;
enable : std_logic;
write : std_logic;
end record;
type itram_out_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE -1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
parity : std_logic;
end record;
type idram_in_type is record
address : std_logic_vector((IOFFSET_BITS + ILINE_BITS -1) downto 0);
data : std_logic_vector(IDWORD_BITS -1 downto 0);
parity : std_logic;
enable : std_logic;
write : std_logic;
end record;
type idram_out_type is record
data : std_logic_vector(IDWORD_BITS -1 downto 0);
parity : std_logic;
end record;
type dtram_in_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE - 1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
parity : std_logic;
enable : std_logic;
write : std_logic;
end record;
type dtram_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
parity : std_logic;
end record;
type ddram_in_type is record
address : std_logic_vector((DOFFSET_BITS + DLINE_BITS -1) downto 0);
data : std_logic_vector(DDWORD_BITS -1 downto 0);
parity : std_logic;
enable : std_logic;
write : std_logic;
end record;
type ddram_out_type is record
data : std_logic_vector(DDWORD_BITS -1 downto 0);
parity : std_logic;
end record;
type icram_in_type is record
itramin : itram_in_type;
idramin : idram_in_type;
end record;
type icram_out_type is record
itramout : itram_out_type;
idramout : idram_out_type;
end record;
type dcram_in_type is record
dtramin : dtram_in_type;
ddramin : ddram_in_type;
end record;
type dcram_out_type is record
dtramout : dtram_out_type;
ddramout : ddram_out_type;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramout : icram_out_type;
dcramout : dcram_out_type;
end record;
type irq_in_type is record
irq : std_logic_vector(15 downto 1);
intack : std_logic;
irl : std_logic_vector(3 downto 0);
end record;
type irq_out_type is record
irl : std_logic_vector(3 downto 0);
end record;
type timers_out_type is record
irq : std_logic_vector(1 downto 0);
tick : std_logic;
wdog : std_logic;
end record;
type uart_in_type is record
rxd : std_logic;
ctsn : std_logic;
end record;
type uart_out_type is record
rxen : std_logic;
txen : std_logic;
flow : std_logic;
irq : std_logic;
rtsn : std_logic;
txd : std_logic;
end record;
type clk_in_type is record
iholdn : std_logic; -- Instruction hold
imdsn : std_logic; -- Instruction memory data strobe
dholdn : std_logic; -- Data hold
dmdsn : std_logic; -- Data memory data strobe
end record;
type clk_out_type is record
clk : std_logic; -- Common clock
cpuclk : std_logic; -- Processor clock
dclk : std_logic; -- Data latch clock
iclk : std_logic; -- Instruction latch clock
holdn : std_logic; -- Instruction latch clock
reset : std_logic; -- Local reset
end record;
type pad_in_type is record
brdyn : std_logic;
bexcn : std_logic;
end record;
type pad_out_type is record
errorn : std_logic;
address : std_logic_vector(27 downto 0);
ramsn : std_logic_vector(3 downto 0);
ramoen : std_logic_vector(3 downto 0);
rwen : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
iosn : std_logic;
oen : std_logic;
read : std_logic;
writen : std_logic;
wdogn : std_logic;
end record;
-- EDAC functions
type edaccorrtype is record
error : std_logic;
merror : std_logic;
data : std_logic_vector(31 downto 0);
cb : std_logic_vector(6 downto 0);
end record;
-- UART numbering
subtype uart_id_type is integer range 0 to 3;
-- iu pipeline control type (defined here to be visible to debug)
type pipeline_control_type is record
inst : std_logic_vector(31 downto 0); -- instruction word
pc : std_logic_vector(31 downto PCLOW); -- program counter
annul : std_logic; -- instruction annul
cnt : std_logic_vector(1 downto 0); -- cycle number (multi-cycle inst)
ld : std_logic; -- load cycle
pv : std_logic; -- PC valid
rett : std_logic; -- RETT indicator
trap : std_logic; -- trap pending flag
tt : std_logic_vector(5 downto 0); -- trap type
rd : std_logic_vector(RABITS-1 downto 0); -- destination register address
end record;
-- iu debug port
type iu_debug_type is record
clk : std_logic;
rst : std_logic;
holdn : std_logic;
de : pipeline_control_type;
ex : pipeline_control_type;
me : pipeline_control_type;
wr : pipeline_control_type;
trap : std_logic;
tt : std_logic_vector(7 downto 0);
end record;
end;
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