ddr_sdram.cmp

这个是基于NIOS II的FPGA平台的一个CF卡的接口模块

-- Generated by DDR SDRAM Controller 3.2.0 [Altera, IP Toolbench v1.2.9 build43]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
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-- net list, support information, device programming or simulation file, or
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component ddr_sdram
	PORT (
		clk	: IN STD_LOGIC;
		write_clk	: IN STD_LOGIC;
		reset_n	: IN STD_LOGIC;
		local_read_req	: IN STD_LOGIC;
		local_write_req	: IN STD_LOGIC;
		local_addr	: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		local_wdata	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_be	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		local_ready	: OUT STD_LOGIC;
		local_rdata	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		local_rdata_valid	: OUT STD_LOGIC;
		clk_to_sdram	: OUT STD_LOGIC;
		clk_to_sdram_n	: OUT STD_LOGIC;
		ddr_cs_n	: OUT STD_LOGIC;
		ddr_cke	: OUT STD_LOGIC;
		ddr_a	: OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
		ddr_ba	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_ras_n	: OUT STD_LOGIC;
		ddr_cas_n	: OUT STD_LOGIC;
		ddr_we_n	: OUT STD_LOGIC;
		ddr_dm	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
		ddr_dq	: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		ddr_dqs	: INOUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
end component;