📄 leonlib.vhd
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-----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leonlib
-- File: leonlib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: package containing LEON
------------------------------------------------------------------------------
-- Version control:
-- 16-08-1999: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package leonlib is
component leon
port (
resetn : in std_logic;
Clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(6 downto 0);
ramsn : out std_logic_vector(3 downto 0);
ramoen : out std_logic_vector(3 downto 0);
rwen : out std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : out std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
pio : inout std_logic_vector(15 downto 0);
wdogn : out std_logic;
-- pragma translate_off
debug : out iu_debug_type
-- pragma translate_on
);
end component;
end;
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