leon.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	leon
-- File:	leon.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Complete processor
------------------------------------------------------------------------------
-- Version control:
-- 13-03-1998:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;

entity leon is
  port (
    resetn   : in  std_logic;
    clk      : in  std_logic;
    errorn   : out std_logic;

    address  : out std_logic_vector(27 downto 0);
    data     : inout std_logic_vector(31 downto 0);
    cb       : inout std_logic_vector(6 downto 0);
    ramsn    : out std_logic_vector(3 downto 0);
    ramoen   : out std_logic_vector(3 downto 0);
    rwen     : out std_logic_vector(3 downto 0);
    romsn    : out std_logic_vector(1 downto 0);
    iosn     : out std_logic;
    oen      : out std_logic;
    read     : out std_logic;
    writen   : out std_logic;
    brdyn    : in  std_logic;
    bexcn    : in  std_logic;

    pio      : inout std_logic_vector(15 downto 0);
    wdogn    : out std_logic
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
  );
end; 

architecture rtl of leon is

component mcore
  port (
    rst      : in  std_logic;
    clk      : in  std_logic;
    error    : out std_logic;
    memi     : in  memory_in_type;
    memo     : out memory_out_type;
    ioi      : in  io_in_type;
    ioo      : out io_out_type
-- pragma translate_off
    ;debug  : out iu_debug_type
-- pragma translate_on
);
end component; 

component pads
  port (
  clki	  : in    std_logic;
  clko	  : out   std_logic;
  resetni : in    std_logic;
  resetno : out   std_logic;
  errorn  : in    std_logic;
  data    : inout std_logic_vector(31 downto 0);
  cb      : inout std_logic_vector(6 downto 0);
  piol    : inout std_logic_vector(15 downto 0);
  padin	  : in    pad_in_type;
  padout  : out   pad_out_type;
  memi	  : out   memory_in_type;
  memo	  : in    memory_out_type;
  ioi	  : out	io_in_type;
  ioo	  : in 	io_out_type
);
end component; 
 
signal clko, resetno, errorno : std_logic;
signal memi     : memory_in_type;
signal memo     : memory_out_type;
signal ioi      : io_in_type;
signal ioo      : io_out_type;
signal padin	: pad_in_type;
signal padout	: pad_out_type;

begin

  mcore0  : mcore  
  port map (
    rst    => resetno,
    clk    => clko, 
    error  => errorno,
    memi   => memi,
    memo   => memo,
    ioi    => ioi,
    ioo    => ioo
-- pragma translate_off
    ,debug  => debug
-- pragma translate_on
  );

  pads0  : pads
  port map (
    clki 	=> clk, 
    clko 	=> clko, 
    resetni	=> resetn,
    resetno	=> resetno,
    errorn	=> errorno,
    data	=> data,
    cb		=> cb,
    piol	=> pio,
    padin	=> padin,
    padout	=> padout,
    memi 	=> memi,
    memo 	=> memo,
    ioi  	=> ioi,
    ioo  	=> ioo
  );

  padin.brdyn      <= brdyn;
  padin.bexcn	   <= bexcn;

  address	<= padout.address;
  ramsn		<= padout.ramsn;
  ramoen	<= padout.ramoen;
  romsn		<= padout.romsn;
  rwen		<= padout.rwen;
  read		<= padout.read;
  writen	<= padout.writen;
  oen		<= padout.oen;
  iosn		<= padout.iosn;
  errorn	<= padout.errorn;
  wdogn		<= padout.wdogn;

end ;