sum.vhd

实现DDS频率可调得VHDL程序

--SUM.VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM IS
	PORT(K:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		CLK:IN STD_LOGIC;
		EN:IN STD_LOGIC;
		RESET:IN STD_LOGIC;
		OUT1:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
		--N:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY SUM;
ARCHITECTURE ONE OF SUM IS
	SIGNAL TEMP : STD_LOGIC_VECTOR(15 DOWNTO 0);
	SIGNAL N : STD_LOGIC_VECTOR(15 DOWNTO 0);
	BEGIN
	PROCESS (CLK,EN,RESET) IS
	BEGIN
	N(15 DOWNTO 8)<=K(7 DOWNTO 0);
	N(7 DOWNTO 0)<="00000000";
	
	IF RESET='1' THEN
		TEMP<= (OTHERS =>'0');
		ELSE
			IF CLK'EVENT AND CLK='1' THEN
				IF EN='1' THEN
					TEMP<=TEMP+N;
				END IF;
			END IF;
	END IF;
	OUT1 <= TEMP;
	--OUT1 <=OUT2(15 DOWNTO 8);
	 END PROCESS;
END ARCHITECTURE ONE;