dma.vhd

一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码

-----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: 	dma
-- File:	dma.vhd
-- Author:	Jiri Gaisler - ESA/ESTEC
-- Description:	Dummy DMA controller. Shows how to connect the memory
--		controller DMA port. Can generate burst read or write
--		transfers. See dma.c on how to program the registers.
--		Does not generate any logic when synthesised.
------------------------------------------------------------------------------
-- Version control:
-- 17-02-1999:	First implemetation
-- 26-09-1999:	Release 1.0
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.config.all;
use work.iface.all;
use work.macro.all;

entity dma is
  port (
    rst    : in  std_logic;
    clk    : in  std_logic;
    pbi    : in  pbus_in_type;
    mcmi   : out memory_dma_in_type;
    mcmo   : in  memory_dma_out_type
  );
end;      

architecture behav of dma is

type dma_type is record
  address          : std_logic_vector(31 downto 0); 
  data             : std_logic_vector(31 downto 0);
  asi              : std_logic_vector(3 downto 0);
  size             : std_logic_vector(1 downto 0);
  length           : std_logic_vector(7 downto 0);
  burst            : std_logic;
  read             : std_logic;
  req              : std_logic;
end record;

signal r, ri : dma_type;

begin

  ctrl: process(pbi, mcmo, r)
  variable v : dma_type;
  begin

    v.address := (others => '0'); v.data := (others => '0');
    v.asi := (others => '0'); v.size := (others => '0');
    v.burst := '0'; v.read := '0'; v.req := '0';

-- pragma translate_off

    if rst = '1' then v := r; end if;

    if ((pbi.enable and not pbi.read) = '1') then
      case pbi.address is
      when "011010" => v.address := pbi.data; v.data := not pbi.data;
      when "011011" => v.asi := pbi.data(3 downto 0);
        v.size := pbi.data(5 downto 4); v.burst := pbi.data(6);
        v.read := pbi.data(7); v.length := pbi.data(15 downto 8);
        v.req := pbi.data(16);
      when others => null;
      end case;
    end if;

    if mcmo.ready = '1' then 
      v.length := v.length - 1;
      v.data := r.data + 1; 
      if r.length = "00000010" then v.burst := '0'; end if;
      if r.length = "00000001" then v.req := '0'; end if;
    end if;


-- pragma translate_on

    ri <= v;


    mcmi.address <= r.address;
    mcmi.data <= v.data;
    mcmi.asi <= r.asi;
    mcmi.size <= r.size;
    mcmi.burst <= r.burst;
    mcmi.read <= r.read;
    mcmi.req <= r.req;

  end process;


  regs : process(clk, ri)
  begin
-- pragma translate_off
    if clk'event and clk = '1' then
-- pragma translate_on
      r <= ri;
-- pragma translate_off
    end if;
-- pragma translate_on
  end process;

end;