dds.vhd

实现DDS频率可调得VHDL程序

--DDS.VHDL
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
	PORT(M:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		EN:IN STD_LOGIC;
		RESET:IN STD_LOGIC;
		CLK:IN STD_LOGIC;
		Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DDS;
ARCHITECTURE ART OF DDS IS
	COMPONENT SUM IS
		PORT (K:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			EN:IN STD_LOGIC;
			RESET:IN STD_LOGIC;
			CLK:IN STD_LOGIC;
			OUT1:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
	END COMPONENT SUM;
	--COMPONENT REG1 IS
	--	PORT (D:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	--			CLK:IN STD_LOGIC;
	--			Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
	--END COMPONENT REG1;
	COMPONENT ROM IS
		PORT (	inclock	:IN STD_LOGIC;
				address:IN STD_LOGIC_VECTOR (9 DOWNTO 0);
				q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT ROM;
	--COMPONENT REG2 IS
	--	PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	--		CLK:IN STD_LOGIC;
	--		Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	--END COMPONENT REG2;
	SIGNAL S1:STD_LOGIC_VECTOR(15 DOWNTO 0);
	--SIGNAL S2:STD_LOGIC_VECTOR(15 DOWNTO 0);
	--SIGNAL S3:STD_LOGIC_VECTOR(9 DOWNTO 0);
	--SIGNAL S4:STD_LOGIC_VECTOR(7 DOWNTO 0);
	BEGIN
	--S3(9 DOWNTO 0)<=S2(15 DOWNTO 6);
	
	U0:SUM PORT MAP(K=>M,CLK=>CLK,EN=>EN,RESET=>RESET,OUT1=>S1);
	--U1:REG1 PORT MAP (D=>S1,CLK=>CLK,Q=>S2);
	U2:ROM PORT MAP (address=>S1(15 DOWNTO 6),inclock =>CLK,q =>Q);
	--U3:REG2 PORT MAP (D=>S4,CLK=>CLK,Q=>Q);
	END ARCHITECTURE ART;