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Logic Analyzer 的代码
v3mux1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity v3mux1 is port
(
clk :in std_logic;
decodein1,decodein2,decodein3 :in std_logic_vector(6 downto 0);
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
FWORD : IN S
modem.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY Modem IS
PORT (
Reset : IN STD_LOGIC; -- Master reset
Clk16X : IN STD_LOGIC; -- UART int
topfile.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY TOPFILE IS
PORT(
UTO_Clock :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s005br is
port(
clk : in vl_logic;
nrst : in vl_logic;
a : in vl_logic_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s006br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s002br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s003br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s001br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
mc8051_ramx_.vhd
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