_primary.vhd

来自「altera i2c host/device」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity m3s002br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        softreset       : in     vl_logic;
        srclkenab       : in     vl_logic;
        opclkenab       : in     vl_logic;
        intsda          : in     vl_logic;
        writedata       : in     vl_logic_vector(7 downto 0);
        openab          : in     vl_logic;
        srload          : in     vl_logic;
        openab2         : in     vl_logic;
        aak             : in     vl_logic;
        sendack         : in     vl_logic;
        assertda        : in     vl_logic;
        shiftreg        : out    vl_logic_vector(7 downto 0);
        ack             : out    vl_logic;
        osda            : out    vl_logic
    );
end m3s002br;