_primary.vhd

来自「altera i2c host/device」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity m3s010br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        softreset       : in     vl_logic;
        starttfer       : in     vl_logic;
        cleartfer       : in     vl_logic;
        step            : in     vl_logic;
        iflg            : in     vl_logic;
        intscl          : in     vl_logic;
        tferdata        : out    vl_logic;
        tferack         : out    vl_logic;
        tfercomp        : out    vl_logic;
        sampaddr        : out    vl_logic;
        enopenab2       : out    vl_logic
    );
end m3s010br;