modem.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY Modem IS
  PORT (
    Reset      : IN  STD_LOGIC; -- Master reset
    Clk16X     : IN  STD_LOGIC; -- UART internal clock
    -- 寄存器
    MSR        : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Modem Status Reg
    MCR        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0); -- Modem Control Reg
-- MSR的上升沿的读选通
MsrRDn_re  : IN  STD_LOGIC; -- pulse indicating rising OF MsrRDn_r
    -- Modem接口
    DCDn       : IN  STD_LOGIC; -- Data Carrier Detect
    CTSn       : IN  STD_LOGIC; -- Clear To Send
    DSRn       : IN  STD_LOGIC; -- Data Set Ready
    RIn        : IN  STD_LOGIC; -- Ring Indicator
    DTRn       : OUT STD_LOGIC; -- Data Terminal Ready
    RTSn       : OUT STD_LOGIC  -- Request To Send
  );
END Modem;

ARCHITECTURE Modem_arch OF Modem IS

  SIGNAL MSReg   : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL CTSn1   : STD_LOGIC; -- Delayed version OF CTSn
  SIGNAL DSRn1   : STD_LOGIC; -- Delayed version OF DSRn
  SIGNAL DCDn1   : STD_LOGIC; -- Delayed version OF DCDn
  SIGNAL RIn1    : STD_LOGIC; -- Delayed version OF RIn

begin

   DTRn <= not MCR(0);
   RTSn <= not MCR(1);

--------------------------------------------------------------------------------
--      Modem状态寄存器设置
--------------------------------------------------------------------------------

  MSR <= MSReg;

  Modem_Stat_Proc: PROCESS(Reset, Clk16X)
  begin
    IF (Reset='1') THEN
      MSReg <= (others=>'0');
      CTSn1 <= '1';
      DSRn1 <= '1';
      DCDn1 <= '1';
      RIn1 <= '1';
    ELSIF rising_edge(Clk16X) THEN
      CTSn1 <= CTSn; -- Delay OF CTSn
      DSRn1 <= DSRn; -- Delay OF DSRn
      DCDn1 <= DCDn; -- Delay OF DCDn
      RIn1 <= RIn;   -- Delay OF RIn
      IF (MsrRDn_re='1') THEN
        MSReg <= (others=>'0');
      else
        MSReg(0) <= MSReg(0) OR (CTSn1 xor CTSn);     -- 表明DCDn改变
        MSReg(1) <= MSReg(1) OR (DSRn1 xor DSRn);     -- 表明DSRn 改变
        MSReg(2) <= MSReg(2) OR ((not RIn1) and RIn);    -- RI的上升沿
        MSReg(3) <= MSReg(3) OR (DCDn1 xor DCDn);     -- 表明DCDn改变
        MSReg(4) <= not CTSn; -- Compliment OF CTSn
        MSReg(5) <= not DSRn; -- Compliment OF DSRn
        MSReg(6) <= not RIn;  -- Compliment OF RIn
        MSReg(7) <= not DCDn; -- Compliment OF DCDn
      END IF;
    END IF;
  END PROCESS Modem_Stat_Proc;

END Modem_arch;