_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s003br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        intscl          : in     vl_logic;
        intsda          : in     vl_logic;
        readdata        : in     vl_logic_vector(7 downto 0);
        ack             : in     vl_logic;
        slaveaddr       : in     vl_logic_vector(6 downto 0);
        extslaveaddr    : in     vl_logic_vector(7 downto 0);
        gcenab          : in     vl_logic;
        enab            : in     vl_logic;
        aak             : in     vl_logic;
        sampaddr        : in     vl_logic;
        arbdataenab     : in     vl_logic;
        arbackenab      : in     vl_logic;
        srclkenab       : in     vl_logic;
        busbusy         : out    vl_logic;
        startdet        : out    vl_logic;
        stopdet         : out    vl_logic;
        arblost         : out    vl_logic;
        slave7det       : out    vl_logic;
        slave101det     : out    vl_logic;
        slave102det     : out    vl_logic;
        gencalldet      : out    vl_logic;
        extaddrdet      : out    vl_logic
    );
end m3s003br;