topfile.vhd

VHDL的例子

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;

ENTITY TOPFILE IS
	PORT(
UTO_Clock					: IN STD_LOGIC;	--用户的输入时钟作为参考时钟								
	--utopia 接收接口信号
		RxAddr						: IN STD_LOGIC_VECTOR(4 DOWNTO 0);	
		Rxdata						: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		RxENB				   		: IN STD_LOGIC;
		RxCLAV						: OUT STD_LOGIC;
		RxSoc			   			: OUT STD_LOGIC;   
	--UTOPIA 发送接口模块		
    		TxAddr						: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		TxEnb						: IN STD_LOGIC;
		TxClav						: OUT STD_LOGIC;
		Txdata						: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		TxSoc						: IN STD_LOGIC;		
	--微处理器接口信号
		D	         					: INOUT	STD_LOGIC_VECTOR(1 DOWNTO 0);
    		BA          	 				: IN  	STD_LOGIC_VECTOR(24 TO 31);
		BCTL0						: IN 	STD_LOGIC;					
		CS6							: IN  	STD_LOGIC	
		);
END TOPFILE;

ARCHITECTURE structure OF TOPFILE IS

	SIGNAL WRCLAV		       	: STD_LOGIC;
	SIGNAL RDCLAV		       	: STD_LOGIC;
   	SIGNAL WR			         : STD_LOGIC;
	SIGNAL RD			         : STD_LOGIC;
	SIGNAL FIFO_RX_DATA		   	: STD_LOGIC_VECTOR(15 DOWNTO 0);
	SIGNAL FIFO_TX_DATA		   	: STD_LOGIC_VECTOR(15 DOWNTO 0);
	SIGNAL TXCLAV_S				: STD_LOGIC;
	SIGNAL RXCLAV_S				: STD_LOGIC;
	SIGNAL RxSoc_S				: STD_LOGIC;
	SIGNAL Clock				   	: STD_LOGIC;
	SIGNAL ResetB				   	: STD_LOGIC;
	SIGNAL RXDATA_S				: STD_LOGIC_VECTOR(15 DOWNTO 0);

  COMPONENT Tx_Sla
	PORT(			
			Clock			   : IN  STD_LOGIC;			
			TxAddr               : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
			TxEnb                : IN  STD_LOGIC;
			TxClav  			   : OUT STD_LOGIC;
			TxSoc 			   : IN STD_LOGIC;
    		Txdata				   : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
     		ResetB			   : IN  STD_LOGIC;
			Wrclav 			   : IN  STD_LOGIC;
			Write_en			   : OUT STD_LOGIC;
			In_Data		  	   : OUT  STD_LOGIC_VECTOR(15 DOWNTO 0)	
			);
 END COMPONENT;

  COMPONENT Rx_Sla
	PORT(				
			RxSoc 					: OUT 	 STD_LOGIC;
			RxClock	   				: IN 		 STD_LOGIC; --CLK FROM 8260
			Rxdata					: OUT 	 STD_LOGIC_VECTOR(15 DOWNTO 0);
			RxAddr               		: IN 		 STD_LOGIC_VECTOR(4 DOWNTO 0);
			RxClav  				  	: OUT	 STD_LOGIC;
			RxEnb                		: IN		 STD_LOGIC;
     		Out_data					: IN		 STD_LOGIC_VECTOR(15 DOWNTO 0);
			Read_en				  	: OUT	 STD_LOGIC;
			ResetB					: IN  	 STD_LOGIC;
			RD_AVAIL				: IN  	 STD_LOGIC;

			GCLK					: IN 		 STD_LOGIC;	
			D	         				: INOUT	 STD_LOGIC_VECTOR(1 DOWNTO 0);
      		BA      		     		: IN  	 STD_LOGIC_VECTOR(24 TO 31);
			BCTL0					: IN 		 STD_LOGIC;		
			CS6			 			: IN  	 STD_LOGIC
			);
 END COMPONENT;

  COMPONENT FIFO
	Port ( 
			clk,reset,wr,rd				: IN		STD_LOGIC;
	          din						: IN 		STD_LOGIC_VECTOR(15 DOWNTO 0);
			 cell_wr,cell_rd				: OUT	STD_LOGIC;
			 dout						: OUT 	STD_LOGIC_VECTOR(15 DOWNTO 0)
                      );                     
 END COMPONENT;
	COMPONENT UP
			PORT(
			GCLK					: IN 		STD_LOGIC;
			D	         				: INOUT	STD_LOGIC_VECTOR(1 DOWNTO 0);
      		BA           				: IN  	STD_LOGIC_VECTOR(24 TO 31);
			BCTL0					: IN 		STD_LOGIC;									CS6			 			: IN  	STD_LOGIC;
			RESETB					: OUT   	STD_LOGIC
         );
 END COMPONENT;
BEGIN
IBUF_1:  IBUF                           
PORT MAP ( I => UTO_Clock, O => Clock);

TX_ctl: Tx_Sla
		PORT MAP(		
					Clock=>Clock ,
					TxAddr => TxAddr,
					TxEnb => TxEnb,
					TxClav => TXCLAV_S,
					TxSoc => TxSoc,
					Txdata => Txdata,					
					ResetB => ResetB,
					Wrclav=>WRCLAV,
					Write_en=>WR,
					In_Data=>FIFO_RX_DATA					
					);
Rx_ctl: Rx_Sla 
				PORT MAP(
				   	RxClock =>Clock,
					RxAddr => RxAddr,
					RxENB => RxEnb,
					RxCLAV => RXCLAV_S,
					RxSoc => RxSoc_S,
					Rxdata => RXDATA_S,					
					ResetB => ResetB,
					RD_AVAIL=>RDCLAV,
					Read_en=>RD,
					Out_data=>FIFO_TX_DATA,
					GCLK =>GCLK,
					D=>D,
					BA=>BA,
					BCTL0=>BCTL0 ,   	
					CS6=>CS6
					);
FIFO: FIFO
			PORT MAP(
					cell_wr=>WRCLAV,
					cell_rd=>RDCLAV,
					din=>FIFO_RX_DATA,
					dout=>FIFO_TX_DATA ,
   					clk	=>Clock,
					reset => ResetB,
					wr=>WR,
					rd=>RD
					);	
UP:UP
			PORT MAP(
					GCLK =>GCLK,
					D=>D,
					BA=>BA,
					BCTL0=>BCTL0 ,   				
					RESETB => ResetB,
					CS6=>CS6
					);	
   	 		 TxClav<=TXCLAV_S;
		    	 RxClav<=RXCLAV_S;
			 RxSoc<=RxSoc_S;
			 RxData<=RXDATA_S;