v3mux1.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity v3mux1 is port
	(
	 clk				:in std_logic;
	 decodein1,decodein2,decodein3	:in std_logic_vector(6 downto 0);
	 dataout		:buffer std_logic_vector(2 downto 0);
	 decodeout	:out std_logic_vector(6 downto 0)
	);
end v3mux1;

architecture archmux of v3mux1 is
begin
	process(clk)
	begin
		if(rising_edge(clk))then
			if(dataout="100")then
				dataout<="001";
				decodeout<=decodein1;
			elsif(dataout="001")then
				dataout<="010";
				decodeout<=decodein2;
			elsif(dataout="010")then
				dataout<="100";
				decodeout<=decodein3;
			else
				dataout<="100";
				decodeout<=decodein3;
			end if;
		end if;
	end process;
end archmux;