translate_2.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity translate_2 is port
	(	
	 	en		:in std_logic;
	 	g		:in std_logic_vector(3 downto 0);
	 	b		:out std_logic_vector(3 downto 0)
	);
end translate_2;

architecture t2 of translate_2 is
begin
	process(g,en)
	begin
		if(en='0')then
			b<="0000";
		else
			case g is
				when "0000"=>b<="0000";
				when "0001"=>b<="0001";
				when "0011"=>b<="0010";
				when "0010"=>b<="0011";
				when "0110"=>b<="0100";
				when "0111"=>b<="0101";
				when "0101"=>b<="0110";
				when "0100"=>b<="0111";
				when "1100"=>b<="1000";
				when "1101"=>b<="1001";
				when "1111"=>b<="1010";
				when "1110"=>b<="1011";
				when "1010"=>b<="1100";
				when "1011"=>b<="1101";
				when "1001"=>b<="1110";
				when "1000"=>b<="1111";
				when others=>null;
			end case;
		end if;
	end process;
end t2;