_primary.vhd

altera i2c host/device

library verilog;
use verilog.vl_types.all;
entity m3s001br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        clkenab         : in     vl_logic;
        maclkenab       : in     vl_logic;
        softreset       : in     vl_logic;
        intscl          : in     vl_logic;
        enab            : in     vl_logic;
        iflg            : in     vl_logic;
        sta             : in     vl_logic;
        stp             : in     vl_logic;
        aak             : in     vl_logic;
        readdata0       : in     vl_logic;
        ack             : in     vl_logic;
        busbusy         : in     vl_logic;
        startdet        : in     vl_logic;
        stopdet         : in     vl_logic;
        arblost         : in     vl_logic;
        slave7det       : in     vl_logic;
        slave101det     : in     vl_logic;
        slave102det     : in     vl_logic;
        gencalldet      : in     vl_logic;
        extaddrdet      : in     vl_logic;
        opclkenab       : out    vl_logic;
        openab          : out    vl_logic;
        assertda        : out    vl_logic;
        sendack         : out    vl_logic;
        setiflg         : out    vl_logic;
        clearsta        : out    vl_logic;
        clearstp        : out    vl_logic;
        srload          : out    vl_logic;
        sampaddr        : out    vl_logic;
        arbdataenab     : out    vl_logic;
        arbackenab      : out    vl_logic;
        status          : out    vl_logic_vector(7 downto 3);
        oscl            : out    vl_logic;
        openab2         : out    vl_logic
    );
end m3s001br;