_primary.vhd

来自「altera i2c host/device」· VHDL 代码 · 共 32 行

library verilog;
use verilog.vl_types.all;
entity m3s005br is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        a               : in     vl_logic_vector(2 downto 0);
        di              : in     vl_logic_vector(7 downto 0);
        wr              : in     vl_logic;
        sel             : in     vl_logic;
        readdata        : in     vl_logic_vector(7 downto 0);
        status          : in     vl_logic_vector(7 downto 3);
        setiflg         : in     vl_logic;
        clearsta        : in     vl_logic;
        clearstp        : in     vl_logic;
        ccr             : out    vl_logic_vector(6 downto 0);
        slaveaddr       : out    vl_logic_vector(6 downto 0);
        extslaveaddr    : out    vl_logic_vector(7 downto 0);
        writedata       : out    vl_logic_vector(7 downto 0);
        enab            : out    vl_logic;
        gcenab          : out    vl_logic;
        sta             : out    vl_logic;
        stp             : out    vl_logic;
        iflg            : out    vl_logic;
        aak             : out    vl_logic;
        da              : out    vl_logic_vector(7 downto 0);
        noe             : out    vl_logic;
        intr            : out    vl_logic;
        softreset       : out    vl_logic
    );
end m3s005br;