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Logic Analyzer 的代码
dmtxdrv.vhd
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-- DMtxDrv (Dot Matrix Driver)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c / 12, Jun., 2005
--
--------------------
regdmtxdrv.vhd
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-- regDMtxDrv (DmtxDrv /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c / 11, Jun., 2005
--
-----------
test_regdmtxdrv.vhd
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-- Test module for regDMtxDrv
-- T.Kohno
-- Rev. 0.1.1 / 9, Jun., 2005
--------------------------------------------
regi2cmaster.vhd
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-- regI2cMaster (i2c Master Unit /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c / 16, Jun., 2005
--
-
regi2cslave.vhd
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-- regI2cSlave (i2c Slave Unit /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 0.5.0c / 16, Jun., 2005
--
---
clock_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;component cnt60 is
port(ch,cl : buffer std_logic_vector (3 downto 0);
clk : in std_logic ;
carry: buffer std_logic
);
end component
use
system.vhd
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity system is
port(reset:in std_logic;
on_off:in std_logic;
cl
system.txt
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity system is
port(reset:in std_logic;
on_off:in std_logic;
cl
dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR
yiwei.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins