regdmtxdrv.vhd

DesignWave 2005 8 Verilog Example

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-- regDMtxDrv (DmtxDrv /w register I/F)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c  / 11, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity regDMtxDrv is
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;

			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0)
			) ;
end regDMtxDrv ;



architecture RTL of regDMtxDrv is

component rif_DMtxDrv
	port(	CLK, nRST			: in std_logic ;
			
			-- Register I/F
			WrEn, RdEn			: in std_logic ;
			Usel				: in std_logic ;  -- Unit select
			Uadrs				: in std_logic_vector(2 downto 0) ;
			Din					: in std_logic_vector(7 downto 0) ;
			Dout				: out std_logic_vector(7 downto 0) ;

			nsyncRST			: out std_logic ;
			-- for MDPGen
			CurCol				: in std_logic_vector(4 downto 0) ;
			Blnk				: in std_logic ;
			CLKDiv				: out std_logic_vector(11 downto 0) ;
			Col2Row				: out std_logic_vector(11 downto 0) ;  -- Row data load latency
			BLCnt				: out std_logic_vector(1 downto 0) ; -- Blank cols. a scan
			-- for VRamIF
			VRHead				: out std_logic_vector(5 downto 0) ;
			VRTail				: out std_logic_vector(5 downto 0) ;
			VRWrp				: out std_logic
			) ;
end component ;

component DMtxDrv
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0) ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- Configurations / Status
			CurCol				: out std_logic_vector(4 downto 0) ;
			Blnk				: out std_logic ;
			--  for MDPGen
			CLKDiv				: in std_logic_vector(11 downto 0) ;
			Col2Row				: in std_logic_vector(11 downto 0) ;  -- Row data load latency
			BLCnt				: in std_logic_vector(1 downto 0) ; -- Blank cols. a scan
			--  for VRamIF
			VRHead				: in std_logic_vector(5 downto 0) ;
			VRTail				: in std_logic_vector(5 downto 0) ;
			VRWrp				: in std_logic
			) ;
--attribute keep			: boolean ;
end component ;


-- connection signals
signal nsyncRST		: std_logic ;
signal CurCol		: std_logic_vector(4 downto 0) ;
signal Blnk			: std_logic ;
signal CLKDiv		: std_logic_vector(11 downto 0) ;
signal Col2Row		: std_logic_vector(11 downto 0) ;  -- Row data load latency
signal BLCnt		: std_logic_vector(1 downto 0) ;  -- Blank cols. a scan
signal VRHead		: std_logic_vector(5 downto 0) ;
signal VRTail		: std_logic_vector(5 downto 0) ;
signal VRWrp		: std_logic ;


begin

-- component instantiation
	rifUNIT: rif_DMtxDrv
		port map (	CLK => CLK, nRST => nRST,
					WrEn => WrEn, RdEn => RdEn,
					Usel => Usel,
					Uadrs => Uadrs,
					Din => Din,
					Dout => Dout,
					nsyncRST => nsyncRST,
					CurCol => CurCol,
					Blnk => Blnk,
					CLKDiv => CLKDiv,
					Col2Row => Col2Row,
					BLCnt => BLCnt,
					VRHead => VRHead,
					VRTail => VRTail,
					VRWrp => VRWrp
					) ;

	DMtxDrvUNIT: DMtxDrv
		generic  map ( COLSIZE => COLSIZE,
					   VBDIV => VBDIV,
					   RAMWAIT => RAMWAIT
					   )
		port map(	CLK => CLK, nRST => nRST,
					nsyncRST => nsyncRST,
					drvRow0 => drvRow0,
					drvRow1 => drvRow1,
					drvCol => drvCol,
					RamAdrs => RamAdrs,
					RamRdEn => RamRdEn,
					RamData => RamData,
					CurCol => CurCol,
					Blnk => Blnk,
					CLKDiv => CLKDiv,
					Col2Row => Col2Row,
					BLCnt => BLCnt,
					VRHead => VRHead,
					VRTail => VRTail,
					VRWrp => VRWrp
					) ;


end RTL ;