dmtxdrv.vhd

DesignWave 2005 8 Verilog Example

--------------------------------------------------------------------------------
-- DMtxDrv (Dot Matrix Driver)
-- Takashi Kohno (DigiCat)
-- Rev. 1.0.0c  / 12, Jun., 2005
--
----------------------------------------
--
-- Copyright (c)   2005   Takashi Kohno
-- This design is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or any later version.
--
-- This design is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
--------------------------------------------------------------------------------
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;


entity DMtxDrv is
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0) ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- Configurations / Status
			CurCol				: out std_logic_vector(4 downto 0) ;
			Blnk				: out std_logic ;
			--  for MDPGen
			CLKDiv				: in std_logic_vector(11 downto 0) ;
			Col2Row				: in std_logic_vector(11 downto 0) ;	-- Row data load latency
			BLCnt				: in std_logic_vector(1 downto 0) ;		-- Blank cols. a scan
			--  for VRamIF
			VRHead				: in std_logic_vector(5 downto 0) ;
			VRTail				: in std_logic_vector(5 downto 0) ;
			VRWrp				: in std_logic
			) ;
end DMtxDrv ;


architecture RTL of DMTxDrv is

component MDPGen
	generic ( COLSIZE			: integer := 3
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Matrix Drivers
			drvRow0				: out std_logic_vector(7 downto 0) ;
			drvRow1				: out std_logic_vector(7 downto 0) ;
			drvCol				: out std_logic_vector(COLSIZE * 8 - 1 downto 0) ;

			-- Row data generator I/F
			DIReq				: out std_logic ;  -- Request strobe for DotInt
			BKRep				: out std_logic ;
			DotInt				: in std_logic_vector(63 downto 0) ;  -- Dot Intesity 8bits x 8
			
			-- Configurations
			ColNo				: out std_logic_vector(4 downto 0) ;
			Blnk				: out std_logic ;
			CLKDiv				: in std_logic_vector(11 downto 0) ;
			Col2Row				: in std_logic_vector(11 downto 0) ;  -- Row data load latency
			BLCnt				: in std_logic_vector(1 downto 0)  -- Blank cols. a scan
			) ;
end component ;

component VRamIF
	generic ( COLSIZE			: integer := 3 ;
			  VBDIV				: integer := 1 ;
			  RAMWAIT			: integer := 1  -- 0 to 7
			  ) ;
	port(	CLK, nRST			: in std_logic ;
			nsyncRST			: in std_logic ;

			-- Ram I/F
			RamAdrs				: out std_logic_vector(5 + VBDIV downto 0) ;
			RamRdEn				: out std_logic ;
			RamData				: in std_logic_vector(64 / (2 ** VBDIV) - 1 downto 0) ;

			-- MDPGen I/F
			DIReq				: in std_logic ;  -- Request strobe for DotInt
			BKRep				: in std_logic ;
			DotInt				: out std_logic_vector(63 downto 0) ;  -- Dot Intensity 8bits x 8
			
			-- Configurations
			VRHead				: in std_logic_vector(5 downto 0) ;
			VRTail				: in std_logic_vector(5 downto 0) ;
			VRWrp				: in std_logic
			) ;
end component ;


-- internal connection signals
signal DIReq		: std_logic ;  -- Request strobe for DotInt
signal BKRep		: std_logic ;
signal DotInt		: std_logic_vector(63 downto 0) ;  -- Dot Intesity data 8bits x 8


begin

-- component instantiation
	DisplayDriver: MDPGen
		generic map ( COLSIZE => COLSIZE
					  )
		port map (	CLK => CLK, nRST => nRST,
					nsyncRST => nsyncRST,
					drvRow0 => drvRow0,
					drvRow1 => drvRow1,
					drvCol => drvCol,
					DIReq => DIReq,
					BKRep => BKRep,
					DotInt => DotInt,
					ColNo => CurCol,
					Blnk => Blnk,
					CLKDiv => CLKDiv,
					Col2Row => Col2Row,
					BLCnt => BLCnt
					) ;

	VRamDriver: VRamIF
		generic  map ( COLSIZE => COLSIZE,
					   VBDIV => VBDIV,
					   RAMWAIT => 2
					   )
		port map (	CLK => CLK, nRST => nRST,
					nsyncRST => nsyncRST,
					RamAdrs => RamAdrs,
					RamRdEn => RamRdEn,
					RamData => RamData,
					DIReq => DIReq,
					BKRep => BKRep,
					DotInt => DotInt,
					VRHead => VRHead,
					VRTail => VRTail,
					VRWrp => VRWrp
					) ;


end RTL ;