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vhd chapter4_models.vhd
entity STATEMENTS is
port(X,Y,Z: in INTEGER; -- Note that entity ports are
B: out INTEGER); -- always signals.
end STATEMENTS;
architecture PROP_DELAY of STATEMENTS is
signal AS:
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vhd chapter12_models.vhd
--------------------------------------------------------
-- The entity declaration of synthesis example model.
--------------------------------------------------------
entity SYNEX1 is
port (A,
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vhd chapter2_models.vhd
--
-- This example illustrates VHDL
-- constructs that can be translated
-- into an iterative network.
--
entity IPAR is
generic (PROP_DEL:time);
port (
R: in BIT_VECTOR (7 downto 0)
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vhd chapter8_models.vhd
-- Device to compare two binary inputs.
--
entity COM is
generic (D:time);
port (N1, N0, M1, M0: in BIT;
GE, LE, E, G, L: out BIT);
end COM;
--Figure 8.2 Entity specification for de
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vhd chapter9_models.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package FINC is
function INC(X :STD_logic_VECTOR) return std_logic_VECTOR;
end FINC;
package body FINC is
function INC(X : std_logic_VECTOR) retu
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vhd chapter5_models.vhd
entity PAR_TO_SER is
port(LD,SHCLK: in BIT; PARIN: in BIT_VECTOR(0 to 7);
BUSY: inout BIT := '0'; SO: out BIT);
end PAR_TO_SER;
architecture TWO_PROC of PAR_TO_SER is
signal SH_COMP:
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vhd chapter6_models.vhd
use work.funcs.all;
entity REG_SYS is
port(C: in BIT; COM: in BIT_VECTOR(0 to 1);
INP: in BIT_VECTOR(0 to 7));
end REG_SYS;
architecture ALG of REG_SYS is
signal R1,R2: BIT_VECTOR(0 t
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vhd chapter3_models.vhd
entity ONES_CNT is
port (A: in BIT_VECTOR(2 downto 0);
C: out BIT_VECTOR(1 downto 0));
------ Truth Table:
---
-----------------------------
---|A2 A1 A0 | C1 C0 |
-------------
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vhd chapter7_models.vhd
package TIMING_CONTROL is
type TIMING is (MIN,MAX,TYP,DELTA);
constant TIMING_SEL: TIMING := TYP;
function T_CHOICE(TIMING_SEL: TIMING; TMIN,TMAX,TTYP: TIME)
return TIME;
end TIMING_CON