chapter6_models.vhd

James Armstrong VHDL Design , source code

use work.funcs.all;
entity REG_SYS is
  port(C: in BIT; COM: in BIT_VECTOR(0 to 1);
       INP: in BIT_VECTOR(0 to 7));
end REG_SYS;
architecture ALG of REG_SYS is
  signal R1,R2: BIT_VECTOR(0 to 7);
begin
  process(C)
  begin
    if C='1' then
      case COM is
        when "00" => R1 <= INP;
        when "01" => R2 <= INP;
        when "10" => R1 <= ADD8(R1,R2);
        when "11" => R1 <= ADD8(R1,INC8(not(R2)));
      end case;
    end if;
  end process;
end ALG;
--Figure 6.1 Algorithmic model of register system.

architecture DF1 of REG_SYS is
  signal MUX_R1,R1,R2,R2C,R2TC,MUX_ADD,SUM:
         BIT_VECTOR(0 to 7);
  signal D00,D01,D10,D11,R1E: BIT;
begin
  D00 <= not COM(0) and not COM(1);
  D01 <= not COM(0) and COM(1);    ---Command Decoder
  D10 <= COM(0) and not COM(1);
  D11 <= COM(0) and COM(1);
  MUX_R1  <= SUM when D00 = '0' else  --Register 1 Mux INP;
      R1E <= D00 or D10 or D11;       --Register 1
R1_REG: block(R1E = '1' and C='1' and not C'STABLE)
  begin
    R1 <= guarded MUX_R1;
  end block R1_REG;
R2_REG: block(D01 = '1' and C='1' and not C'STABLE)
  begin
    R2 <= guarded INP;             ---Register 2
  end block R2_REG;
  R2C <= not R2;                   ---Complement
  R2TC <= INC8(R2C);               ---Increment
  MUX_ADD <= R2TC when D11 = '1' else
             R2;                   ---Adder Mux
  SUM <= ADD8(R1,MUX_ADD);         ---Adder
end DF1;
--Figure 6.2 Detailed data flow description.

architecture DF2 of REG_SYS is
  signal R1,R2: BIT_VECTOR(0 to 7);
begin
R1_REG: block((COM(0) or not COM(1))='1' and C='1'
              and not C'STABLE)
  begin
    R1 <= guarded
       ADD8(R1,R2) when (COM(0) and not COM(1)) = '1' else
  ADD8(R1,INC8(not(R2))) when (COM(0) and COM(1)) ='1' else
       INP;
  end block R1_REG;
R2_REG: block(( not COM(0) and COM(1)) = '1' and C='1'
              and not C'STABLE)
  begin
    R2 <= guarded INP;
  end block R2_REG;
end DF2;
--Figure 6.3 Concise  data  flow description of register system.

architecture DF3 of REG_SYS is
  signal MUX_R1,R1,R2,R2C,R2TC,MUX_ADD,SUM:
         BIT_VECTOR(0 to 7);
  signal R1E,R2E: BIT;
begin
  MUX_R1 <= SUM when COM(0) = '1' else  ---Register 1 Mux
            INP;
  R1E  <= COM(0) or not COM(1);         ---Register 1
R1_REG: block(R1E = '1' and C='1' and not C'STABLE)
  begin
    R1 <= guarded MUX_R1;
  end block R1_REG;
  R2E <= not R1E;
R2_REG: block(R2E = '1' and C='1' and not C'STABLE)
  begin
    R2 <= guarded INP;             ---Register 2
  end block R2_REG;
  R2C <= not R2;                   ---Complement
  R2TC <= INC8(R2C);               ---Increment
  MUX_ADD <= R2TC when COM(1) = '1' else
             R2;                   ---Adder Mux
  SUM <= ADD8(R1,MUX_ADD);         ---Adder
end DF3;
--Figure 6.4 Detailed data flow description with local decoding

use work.funcs.all;
entity REG_SYS_T is
  generic(MR1DEL,R1EDEL,R1DEL,R2EDEL,R2DEL,
          R2CDEL,R2IDEL,MADDDEL,ADDDEL: TIME);
  port(C: in BIT; COM: BIT_VECTOR(0 to 1);
       INP: in BIT_VECTOR(0 to 7));
begin
  process(C)
    variable COLDT,CNEWT: TIME:= 0 ns;
  begin
    assert not(C'EVENT and C = '1'
      and not COM'STABLE(MADDDEL+ADDDEL+MR1DEL))
      report "COM Set Up Time Failure" severity WARNING;
    if C'EVENT and C = '1' then
    CNEWT := NOW;-- NOW returns the current simulation time.
      assert (CNEWT - COLDT) > (R2DEL + R2CDEL + R2IDEL
                                + MADDDEL + ADDDEL + MR1DEL)
        report "Clock Period Too Short" severity WARNING;
    end if;
    COLDT := CNEWT;
  end process;
end REG_SYS_T;

architecture DF3T of REG_SYS_T is
  signal MUX_R1,R1,R2,R2C,R2TC,MUX_ADD,SUM:
         BIT_VECTOR(0 to 7);
  signal R1E,R2E: BIT;
begin
  MUX_R1 <= SUM after MR1DEL when COM(0) = '1' else
            INP after MR1DEL;
  R1E <= COM(0) or not COM(1) after R1EDEL; ---Register 1
R1_REG: block(R1E = '1' and C='1' and not C'STABLE)
  begin
    R1 <= guarded MUX_R1 after R1DEL;
  end block R1_REG;
  R2E <= not R1E after R2EDEL;
R2_REG: block(R2E = '1' and C='1' and not C'STABLE)
  begin
    R2 <= guarded INP after R2DEL;             ---Register 2
  end block R2_REG;
  R2C <= not R2 after R2CDEL;                  ---Complement
  R2TC <= INC8(R2C) after R2IDEL;              ---Increment
  MUX_ADD <= R2TC after MADDDEL when COM(1) = '1' else
             R2 after MADDDEL;                 ---Adder Mux
  SUM <= ADD8(R1,MUX_ADD) after ADDDEL;        ---Adder
end DF3T;

--Figure 6.6 Register system with timing.
-- The entity declaration of the URISC processor
use work.all;use work.SYSTEM_4.all;
entity URISC is
  generic(ENABLE_DEL,DISBL_DEL,REG_DEL,ADD_DEL,PER,
          COUNT_DEL, ROM_DEL,OR_DEL,AND_DEL,INV_DEL,
          MUX_DEL: TIME);
  port(DATA: inout WORD:="ZZZZZZZZ";
       ADDRESS: inout WORD:="00000001";
       RUN,IO_DAV: in BIT; RDIO,WRITE: inout BIT;
       RDMR,CSMR: out BIT);
end URISC;

-- The architecture of the URISC ------------------------
use work.all;use work.SYSTEM_4.all;
architecture BEHAVIORAL of URISC is
  signal PC1,R,R_NOT,BUS_A,BUS_B,MDR1,MDR: WORD;
  signal PC: WORD:="00000001";
  signal Z,ZERO,ZIN,N,PH1,PH2,R_IN,MDR_IN,N_IN,MAR_IN,
         C_IN,CLK,CLEAR: BIT;
  signal COMP,MDR_OUT,PC_IN,PC_OUT,ZEND,NNEND,READ: BIT;
  signal C: BIT_VECTOR(3 downto 0);
begin
  PC_REG : block (PCIN and PH2='0'and not PH2'stable)
---Insert Code for Program Counter Register ----------
  end block;
  R_REG : block (R_IN='1'and PH2='0'and not PH2'STABLE)
---Insert Code for Register R ------------------------
  end block;
  -------- The Adder ---------------------------------
  BUS_B <=  ADD(BUS_A,R_NOT,C_IN) after ADD_DEL;
  N_REG : block(N_IN= '1' and PH2='0'and not PH2'STABLE)
---Insert Code for Register N-------------------------
  end block;
  Z_REG : block(Z_IN= '1' and PH2='0'and not PH2'STABLE)
---Insert Code for Z Register ------------------------
  end block;
  MDR_REG : block((MDRIN and PH2='0'and not PH2'STABLE)
              or (READ and PH1='0' and not PH1'STABLE))
---Insert Code for Memory Data Register --------------
  end block;
  MAR : block (MAR_IN='1' and PH2='0' and not PH2'STABLE)
---Insert Code for Memory Address Register MAR -------
  end block;
  process
---Insert Code for Internal Two Phase Clocks ---------
  end process;
  -------- The Control Unit -------------------------
---Insert Code for the Control Unit
end BEHAVIORAL;

--Figure 6.18Outline for register level description of the URISC processor.
---------The COUNTER ------------------------------
-- The Counter has a synchronous CLEAR ------------
COUNTER: block (PH1= '0' and not PH1'STABLE )
begin
  C <= guarded "0000" after COUNT_DEL when CLEAR='1' else
               INC_COUNTER(C) after COUNT_DEL;
end block COUNTER;
-------- The microinstructions ROM  ----------------------
ROM: process(C)
  type SQ_ARRAY is array(0 to 8,0 to 8) of BIT;
  constant MEM : SQ_ARRAY:=
-- 0       1    2    3     4     5    6    7     8   COLUMN
MDR_OUT,MAR_IN,N_IN,R_IN,PC_IN,ZEND,C_IN,WRITE,NNEND,micins
(('0',    '1', '0', '0',  '0',  '1', '0', '0',  '0'), --0
 ('1',    '1', '0', '0',  '0',  '0', '0', '0',  '0'), --1
 ('1',    '0', '0', '1',  '0',  '0', '0', '0',  '0'), --2
 ('0',    '1', '0', '0',  '1',  '0', '1', '0',  '0'), --3
 ('1',    '1', '0', '0',  '0',  '0', '0', '0',  '0'), --4
 ('1',    '0', '1', '0',  '0',  '0', '1', '1',  '0'), --5
 ('0',    '1', '0', '0',  '1',  '0', '1', '0',  '0'), --6
 ('0',    '0', '0', '0',  '1',  '0', '1', '0',  '1'), --7
 ('1',    '0', '0', '0',  '1',  '0', '0', '0',  '0'));--8
begin
  MDR_OUT  <=   MEM(INTVAL(C),0) after ROM_DEL;
  MAR_IN   <=   MEM(INTVAL(C),1) after ROM_DEL;
  N_IN     <=   MEM(INTVAL(C),2) after ROM_DEL;
  R_IN     <=   MEM(INTVAL(C),3) after ROM_DEL;
  PC_IN    <=   MEM(INTVAL(C),4) after ROM_DEL;
  ZEND     <=   MEM(INTVAL(C),5) after ROM_DEL;
  C_IN     <=   MEM(INTVAL(C),6) after ROM_DEL;
  WRITE    <=   MEM(INTVAL(C),7) after ROM_DEL;
  NNEND    <=   MEM(INTVAL(C),8) after ROM_DEL;
end process ROM;
LOGIC: block
begin
  ZIN     <=  ZEND;
  ZERO    <=  NOR_BITS(BUS_B) after OR_DEL;
  CLEAR <= (Z and ZEND) or (not N and NNEND) or
           (C = "1000") after AND_DEL+OR_DEL;
  PC_OUT  <=  not MDR_OUT after INV_DEL;
  READ    <= MAR_IN;
  COMP    <= N_IN;
  MDR_IN  <= N_IN;
  RDMR <= READ and not MVL4toBIT(ADDRESS(7)) after AND_DEL;
  RDIO <= READ and MVL4toBIT(ADDRESS(7)) after AND_DEL;
  CSMR    <= not MVL4toBIT(ADDRESS(7)) after INV_DEL;
end block LOGIC;

--Figure 6.20 Microcoded control unit for URISC.
-------- The COUNTER ------------------------------
-- The Counter has a synchronous CLEAR ------------
COUNTER: block (PH1= '0' and not PH1'STABLE )
  begin
    C <= guarded "0000" after COUNT_DEL 
                 when (CLEAR='1'or C="1000") else
         INC_COUNTER(C) after COUNT_DEL;
  end block COUNTER;
  --Hard Wired Control Unit
  --Decoder
  --First Stage Decoding
  ST0 <= not C(2) and not C(1) and not C(0) after AND_DEL;
  ST1 <= not C(2) and not C(1) and C(0) after AND_DEL;
  ST2 <= not C(2) and C(1) and not C(0) after AND_DEL;
  ST3 <= not C(2) and C(1) and  C(0) after AND_DEL;
  ST4 <= C(2) and not C(1) and not C(0) after AND_DEL;
  ST5 <= C(2) and not C(1) and C(0) after AND_DEL;
  ST6 <= C(2) and C(1) and not C(0) after AND_DEL;
  ST7 <= C(2) and C(1) and C(0) after AND_DEL;
  --Second Stage Decoding
  ST07 <= ST0 or ST7 after OR_DEL;
  ST25 <= ST2 or ST5 after OR_DEL;
  ST36 <= ST3 or ST6 after OR_DEL;
  ST57 <= ST5 or ST7 after OR_DEL;
  ST78 <= ST7 or C(3) after OR_DEL;
  --Control Signals
  PC_OUT <= (ST07 or ST36) and not C(3)
             after (OR_DEL + AND_DEL);
  C_IN <= ST36 or ST57 after OR_DEL;
  PC_IN <= ST36 or ST78 after OR_DEL;
  MAR_IN <= not(ST25 or ST78) after (OR_DEL + INV_DEL);
  MDR_OUT <=not PC_OUT after INV_DEL;
  READ <= MAR_IN; COMP <= ST5; N_IN <= ST5; MDR_IN <= ST5;
  WRITE <= ST5; R_IN <= ST2; ZIN <= ST0; ZEND <=ST0;
  NNEND <= ST7;
  --Register and Counter Controls
  ZERO <= NOR_BITS(BUS_B) after OR_DEL;
  CLEAR <= (Z and ZEND) or (not N and NNEND)
            after AND_DEL+OR_DEL;
  RDMR <= READ and not MVL4toBIT(ADDRESS(7)) after AND_DEL;
  RDIO <= READ and MVL4toBIT(ADDRESS(7)) after AND_DEL;
  CSMR <= not MVL4toBIT(ADDRESS(7)) after INV_DEL;
--Figure 6.21 VHDL description of hardwired control unit for URISC