chapter2_models.vhd

来自「James Armstrong VHDL Design , source cod」· VHDL 代码 · 共 29 行

--
-- This example illustrates VHDL 
-- constructs that can be translated 
-- into an iterative network.
--
entity IPAR is
  generic (PROP_DEL:time);
  port (
    R: in BIT_VECTOR (7 downto 0);
    P: out BIT);
end IPAR;
--
-- Model using a FOR loop
--
architecture LOOP4 of IPAR is
begin
  OPAR:process(R)
    variable X: BIT;
  begin
    X:='0';
    for I in 7 downto 0 loop
      X:=X xor R(I);
    end loop;
    P <= X after PROP_DEL;
  end process;
end LOOP4;

--      Figure 2.13