chapter3_models.vhd

James Armstrong VHDL Design , source code

entity ONES_CNT  is
port (A: in BIT_VECTOR(2 downto 0);
      C: out BIT_VECTOR(1 downto 0));

------ Truth Table:
---
-----------------------------
---|A2   A1   A0  |  C1  C0 |
-----------------------------
-- |0    0     0  |  0   0  |
-- |0    0     1  |  0   1  |
-- |0    1     0  |  0   1  |
-- |0    1     1  |  1   0  |
-- |1    0     0  |  0   1  |
-- |1    0     1  |  1   0  |
-- |1    1     0  |  1   0  |
-- |1    1     1  |  1   1  |
-----------------------------
end ONES_CNT;
--Figure 3.1 Commented interface description.

architecture ALGORITHMIC of ONES_CNT is
begin
  process(A)
    variable NUM: INTEGER range 0 to 3;
begin
    NUM := 0;
    for I in 0 to 2 loop
      if A(I) = '1'  then
        NUM := NUM + 1;
      end if;
    end loop;
    case NUM is
      when  0 => C <= "00";
      when  1 => C <= "01";
      when  2 => C <= "10";
      when  3 => C <= "11";
    end case;
  end process;
end ALGORITHMIC;
--Figure 3.2 An algorithmic description of the ones counter.

architecture DATA_FLOW of ONES_CNT  is
  begin
   C(1) <= (A(1) and A(0)) or (A(2) and A(0))
        or (A(2) and A(1));
   C(0) <= (A(2) and not A(1) and not A(0))
        or (not A(2) and not A(1)and A(0))
        or (A(2) and A(1) and A(0))
        or (not A(2) and A(1) and not A(0));
  end DATA_FLOW;
--Figure 3.4 Data flow model of the ones counter.

use work.all;
entity MAJ3 is
  port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end MAJ3;
architecture AND_OR of MAJ3 is
  component AND2C
    port (I1,I2: in BIT; O: out BIT);
  end component;
  component OR3C
    port (I1,I2,I3: in BIT; O: out BIT);
  end component;
  for all: AND2C use entity AND2(BEHAVIOR);
  for all: OR3C use entity OR3(BEHAVIOR);
  signal A1,A2,A3: BIT;
begin
  G1: AND2C
    port map (X(0),X(1),A1);
  G2: AND2C
    port map (X(0),X(2),A2);
  G3: AND2C
    port map (X(1),X(2),A3);
  G4: OR3C
    port map (A1,A2,A3,Z);
end AND_OR;

             --  (a) MAJ3 Description

entity AND2 is
  port (I1,I2: in BIT; O: out BIT);
end AND2;
architecture BEHAVIOR of AND2 is
begin
  O <= I1 and I2;
end BEHAVIOR;

            --   (b) AND2 Description

entity OR3 is
  port (I1,I2,I3: in BIT; O: out BIT);
end OR3;
architecture BEHAVIOR of OR3 is
begin
  O <= I1 or I2 or I3;
end BEHAVIOR;

               --(c) OR3  Description
--Figure 3.6 Structural description of MAJ3.

use work.all;
architecture STRUCTURAL of ONES_CNT is
  component MAJ3C
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
  end component;
  component OPAR3C
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
  end component;
  for all: MAJ3C use entity MAJ3(AND_OR);
  for all: OPAR3C use entity OPAR3(AND_OR);
begin
  COMPONENT_1: MAJ3C
    port map (A,C(1));
  COMPONENT_2: OPAR3C
    port map (A,C(0));
end STRUCTURAL;
--Figure 3.8 Structural architectural body for the ones counter.

entity TEST_BENCH is
end TEST_BENCH;

use WORK.all;
architecture ONES_CNT1 of TEST_BENCH is
  signal A: BIT_VECTOR(2 downto 0);  ----Declare signals
  signal C: BIT_VECTOR(1 downto 0);
  component ONES_CNTA               ----Declare component
    port (A: in BIT_VECTOR(2 downto 0);
          C: out BIT_VECTOR(1 downto 0));
  end component;
 for L1: ONES_CNTA use entity ONES_CNT(ALGORITHMIC);
begin
  L1: ONES_CNTA
    port map(A, C);
  process
  begin
    A <= "000" after 1 ns,
         "001" after 2 ns,
         "010" after 3 ns,
         "011" after 4 ns,
         "100" after 5 ns,
         "101" after 6 ns,
         "110" after 7 ns,
         "111" after 8 ns;
    wait;
  end process;
end ONES_CNT1;
--Figure 3.9 TEST_BENCH for entity ONES_CNT.

entity GUARD_EXAMP is
    port(I1,I2,CON: in BIT; O1,O2: out BIT);
  end GUARD_EXAMP;

  architecture DF of GUARD_EXAMP is
    begin
     B:block(CON = '1')
      begin
       O1 <= guarded I1;
       O2 <= I2 ;
     end block B;
  end DF;
--Figure 3.12 Guarded Block Example

entity PULSE_GEN is
  generic(N: INTEGER; PER: TIME);
  port(START:in BIT; PGOUT:out BIT_VECTOR(N-1 downto 0);
       SYNC:inout BIT);
end PULSE_GEN;
architecture ALG of PULSE_GEN is
  function INT_TO_BIN (INPUT : INTEGER;N : POSITIVE)
    return BIT_VECTOR is
    variable FOUT: BIT_VECTOR(0 to N-1);
    variable TEMP_A: INTEGER:= 0;
    variable TEMP_B: INTEGER:= 0;
  begin  -- Begin function code.
    TEMP_A := INPUT;
    for I in N-1 downto 0 loop
      TEMP_B := TEMP_A/(2**I);
      TEMP_A := TEMP_A rem (2**I);
      if (TEMP_B = 1) then
        FOUT(N-1-I) := '1';
      else
        FOUT(N-1-I) := '0';
      end if;
    end loop;
    return FOUT;
  end INT_TO_BIN;
begin  -- Begin architecture body
  process(START,SYNC)
    variable CNT: INTEGER:= 0;
  begin  -- Begin process
    if START'EVENT and START='1' then
      CNT := 2**N-1;
    end if;
    PGOUT <=  INT_TO_BIN(CNT,N) after PER;
    if CNT /= -1 and START ='1' then
      SYNC <= not SYNC after PER;
      CNT := CNT -1;
    end if;
  end process;
end ALG;
--Figure 3.25 Function to convert an INTEGER type to type BIT_VECTOR.

procedure ADD(A,B: in BIT_VECTOR; CIN: in BIT;
              SUM: out BIT_VECTOR; COUT: out BIT) is
  variable SUMV,AV,BV: BIT_VECTOR(A'LENGTH-1 downto 0);
  variable CARRY: BIT;
begin
  AV := A;
  BV := B;
  CARRY := CIN;
  for I in 0 to SUMV'HIGH loop
    SUMV(I) := AV(I) xor BV(I) xor CARRY;
    CARRY := (AV(I) and BV(I)) or (AV(I) and CARRY)
              or (BV(i) and CARRY);
  end loop;
  COUT := CARRY;
  SUM := SUMV;
end ADD;
--Figure 3.26 Procedure to add bit vectors.

function "and" (L, R: MVL4) return MVL4 is
   -- Declare a two-dimensional table type.
   type MVL4_TABLE is array (MVL4, MVL4) of MVL4;
   -- truth table for "and" function
   constant table_AND: MVL4_TABLE :=
--  --------------------------------
--  |  X    0    1    Z  |
--  --------------------------------
    (('X', '0', 'X', 'X'),  -- | X |
     ('0', '0', '0', '0'),  -- | 0 |
     ('X', '0', '1', 'X'),  -- | 1 |
     ('X', '0', 'X', 'X')); -- | Z |
begin
  return table_AND(L, R);
end "and";
--Figure 3.27 Overloading the and function.

function INTVAL (VAL: MVL4_VECTOR)
    return INTEGER is
  variable SUM: INTEGER:= 0;
begin
  for  N in VAL'LOW to VAL'HIGH loop
    assert not(VAL(N) = 'X' or VAL(N) = 'Z')
    report "INTVAL inputs not 0 or 1"
    severity WARNING;
    if  VAL(N) = '1' then
      SUM := SUM + (2**N);
    end if;
  end loop;
  return SUM;
end INTVAL;
--Figure 3.28 Declaration of a function to convert type MVL4_VECTOR
 --to typeINTEGER 

function INTVAL(VAL:BIT_VECTOR) return INTEGER is
  variable SUM: INTEGER:=0;
begin
  for N in VAL'LOW to VAL'HIGH loop
    if VAL(N)='1' then
      SUM := SUM + (2 ** N);
    end if;
  end loop;
  return SUM;
end INTVAL;
--Figure 3.29 Declaration of function to convert type BIT_VECTOR to type INTEGER.

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;.
entity ADD_OVERLOAD is
  port ( A, B, C: in  STD_LOGIC_VECTOR (7 downto 0);
         SUM: out STD_LOGIC_VECTOR (7 downto 0));
end ADD_OVERLOAD;
architecture PACK_SIGNED of ADD_OVERLOAD is
begin
  SUM <=  A + B + C; --This is now 2's-
                     --complement addition
end PACK_SIGNED;
--Figure 3.30 Overloading ADD with signed package.

package SIG is
  signal X: INTEGER:= 1;
end SIG;

use work.SIG.all;
entity Y is
  signal X: INTEGER:= 2;
end Y;

architecture Z of Y is
  signal Z1,Z2,Z3,Z4,Z5: INTEGER:= 0;
  function R return INTEGER is
    variable X: INTEGER := 3;
  begin
    return X; -- Returns value of 3.
  end R;
begin
  B: block
    signal X: INTEGER := 4;
    signal Z6: INTEGER := 0;
  begin
    Z6 <= X + Y.X;  -- Z6 = 6
  end block B;

P1: process
     variable X: INTEGER :=5;
  begin
    Z5 <= X;        -- Z5=5
    wait;
  end process;

  Z1 <= work.SIG.X; -- Z1=1
  Z2 <= X;          -- Z2=2
  Z3 <= R;          -- Z3=3
  Z4 <= B.X;        -- Z4=4