chapter12_models.vhd

James Armstrong VHDL Design , source code

--------------------------------------------------------
-- The entity declaration of synthesis example model.
--------------------------------------------------------
entity SYNEX1 is
  port (A, B, C, D, E: in INTEGER;
        X, Y: out INTEGER);
end SYNEX1;
--------------------------------------------------------
-- The architecture declaration of synthesis example model.
--------------------------------------------------------
architecture HIGH_LEVEL of SYNEX1 is
begin
  X <= E*(A+B+C);
  Y <= (A+C)*(C+D);
end HIGH_LEVEL;
Figure 12.2 Example of algorithmic level VHDL description

entity FSMEX1 is
  port (A, B, C, D, E: in INTEGER;
        CLK: in BIT;
        X, Y: out INTEGER);
end FSMEX1;
--------------------------------------------------------
architecture FSM of FSMEX1 is
  type STATE_TYPE is (S0, S1, S2, S3, S4);
  signal STATE: STATE_TYPE;
  signal R1, R2, R3, R4, R5: INTEGER;
begin
-- Process to update state and perform register transfers.
STATEP: process (CLK)
  begin
    if CLK'event and CLK='1' then
      case STATE is
        when S0 =>
          -- Data Section
          R5 <= E; R4 <= B; R3 <= D; R2 <= C; R1 <= A;
           -- Control Section
          STATE <= S1;
        when S1 =>
          -- Data Section
          R1 <= R1 + R2;
          -- Control Section
          STATE <= S2;
        when S2 =>
          -- Data Section
          R2 <= R2 + R3;
          -- Control Section
          STATE <= S3;
        when S3 =>
          -- Data Section
          R1 <= R4 + R1;
          R4 <= R1 * R2;
          -- Control Section
          STATE <= S4;
        when S4 =>
          -- Data Section
          R3 <= R5 * R1;
          -- Control Section
          STATE <= S0;
      end case;
    end if;
  end process STATEP;
  -- Assign output.
  X <= R3; Y <= R4;
end FSM;
--Figure 12.11 FSM VHDL model for example.

package TYPES is
  attribute ENCODING: STRING;
  type ENUM is (A, B, C, D);
  attribute ENCODING of ENUM: type is "00 01 10 11";
end TYPES;
  ----------------------------------------------------------
use work.TYPES.all;
entity MUX is
  port (X, Y: in BIT;  VECT: in BIT_VECTOR(3 downto 0);
        CHOICE: in ENUM; INDEX: in INTEGER range 3 downto 0;
        Z1, Z2, Z3: out BIT);
end MUX;
  ----------------------------------------------------------
architecture MUX_CONSTRUCTS of MUX is
begin
MUX1: process (CHOICE, X, Y)
  begin
    case CHOICE is
      when A => Z1 <= X;
      when B => Z1 <= Y;
      when C => Z1 <= not X;
      when D => Z1 <= not Y;
    end case;
  end process MUX1;
  ----------------------------------------------------------
MUX2: process (X, Y, VECT)
  begin
    if X = '1' then
      Z2 <= VECT(3);
    elsif Y = '1' then
      Z2 <= VECT(2);
    else
      Z2 <= VECT(1) and VECT(0);
    end if;
  end process MUX2;
  ----------------------------------------------------------
MUX3: process (VECT, INDEX)
  begin
    Z3 <= VECT(INDEX);
  end process MUX3;
end MUX_CONSTRUCTS;
--Figure 12.53 VHDL constructs that map to multiplexer elements.

----------------------------------------------
-- Entity declaration for 4-bit XOR circuit --
----------------------------------------------
entity XOR4 is
  port (A: in BIT_VECTOR (3 downto 0);
        X: out BIT);
end XOR4;
---------------------------------------------------
-- Standard loop definition for circuit behavior.--
---------------------------------------------------
architecture XOR4_LOOP of XOR4 is
begin
  process (A)
    variable X_INT: BIT;
  begin
    X_INT := '0';
    for I in 0 to 3 loop
      X_INT := X_INT xor A(I);
    end loop;
    X <= X_INT;
  end process;
end XOR4_LOOP;
---Figure 12.57 A VHDL program with a simple program loop.

-- Entity declaration for 4-bit XOR circuit--
---------------------------------------------
entity XOR4 is
  port (A: in BIT_VECTOR (3 downto 0);
        X: out BIT);
end XOR4;
-----------------------------------------------------------
-- Space_Time transformation of standard loop definition.--
-----------------------------------------------------------
architecture XOR4_SPACE of XOR4 is
begin
  process (A)
    variable X_INT: BIT_VECTOR (4 downto 0);
  begin
    X_INT(0) := '0';
    for I in 0 to 3 loop
      X_INT(I+1) := X_INT(I) xor A(I);
    end loop;
    X <= X_INT(4);
  end process;
end XOR4_SPACE;
--Figure 12.59 VHDL program obtained by applying a space-time transformation to architecture  -------
 
--XOR4_LOOP.
-- Entity declaration for a 4-bit binary adder. --
--------------------------------------------------
entity ADD4 is
  port (A,B: in BIT_VECTOR (3 downto 0);
        CIN: in BIT;
        S: out BIT_VECTOR (3 downto 0);
        COUT: out BIT);
end ADD4;
-------------------------------------------------------
-- Typical definition of adder using a program loop. --
-------------------------------------------------------
architecture LOOP_ADDER of ADD4 is
begin
  process (A, B, CIN)
    variable CARRY: BIT := '0';
    variable SUM: BIT_VECTOR (3 downto 0);
  begin
    CARRY := CIN;
    for I in 0 to 3 loop
      SUM(I) := A(I) xor B(I) xor CARRY;
      CARRY := (A(I) and B(I)) or (A(I) and CARRY) or
               (B(I) and CARRY);
    end loop;
    S <= SUM;
    COUT <= CARRY;
  end process;
end LOOP_ADDER;
---Figure 12.61 VHDL program for a ripple carry adder.

----------------------------------------------------------
-- Applying space time transformation to LOOP_ADDER-------
-- architecture. --
----------------------------------------------------------
architecture SPACE_ADDER of ADD4 is
begin
  process (A, B, CIN)
    variable CARRY: BIT_VECTOR (4 downto 0) := "00000";
    variable SUM: BIT_VECTOR (3 downto 0);
  begin
    CARRY(0) := CIN;
    for I in 0 to 3 loop
      SUM(I) := A(I) xor B(I) xor CARRY(I);
      CARRY(I+1) := (A(I) and B(I)) or (A(I) and CARRY(I))
                    or (B(I) and CARRY(I));
    end loop;
    S <= SUM;
    COUT <= CARRY(4);
  end process;
end SPACE_ADDER;
--Figure 12.63 Result of applying a space-time transformation to architecture LOOP_ADDER.

-- Use of functions to define the adder.   --
---------------------------------------------
architecture FUNCTION_ADDER of ADD4 is
  -- Function to compute the sum output
  function FA_S (AIN, BIN, CIN: BIT) return BIT is
  begin
    return AIN xor BIN xor CIN;
  end FA_S;
  -- Function to compute the carry output
  function FA_C (AIN, BIN, CIN: BIT) return BIT is
  begin
    return (AIN and BIN) or (AIN and CIN) or (BIN and CIN);
  end FA_C;
begin
  process (A, B, CIN)
    variable CARRY: BIT_VECTOR (4 downto 0) := "00000";
    variable SUM: BIT_VECTOR (3 downto 0) := "0000";
  begin
    CARRY(0) := CIN;
    for I in 0 to 3 loop
      SUM(I) := FA_S(A(I), B(I), CARRY(I));
      CARRY(I+1) := FA_C(A(I), B(I), CARRY(I));
    end loop;
    S <= SUM;
    COUT <= CARRY(4);
  end process;
end FUNCTION_ADDER;
--Figure 12.65 Using functions to represent combinational logic.

---------------------------------------------
-- Use of a procedure to define the adder. --
---------------------------------------------
architecture PROCEDURE_ADDER of ADD4 is
  procedure FA(AIN, BIN, CIN: in BIT;
               SOUT, COUT: out BIT) is
  begin
    SOUT := AIN xor BIN xor CIN;
    COUT := (AIN and BIN) or (AIN and CIN) or 
            (BIN and CIN);
  end FA;
begin
  process (A, B, CIN)
    variable CARRY: BIT_VECTOR (4 downto 0) := "00000";
    variable SUM: BIT_VECTOR (3 downto 0) := "0000";
  begin
    CARRY(0) := CIN;
    for I in 0 to 3 loop
      FA(A(I), B(I), CARRY(I), SUM(I), CARRY(I+1));
    end loop;
    S <= SUM;
    COUT <= CARRY(4);
  end process;
end PROCEDURE_ADDER;
--Figure 12.66 Using procedures to represent combinational logic.