chapter9_models.vhd

James Armstrong VHDL Design , source code

library IEEE;
use IEEE.std_logic_1164.all;
package FINC is

function INC(X :STD_logic_VECTOR) return std_logic_VECTOR;

end FINC;
package body FINC is
  function INC(X : std_logic_VECTOR) return std_logic_VECTOR is
   variable XV: std_logic_VECTOR(X'LENGTH-1 downto 0);
  begin
   XV := X;
   for I in 0 to XV'HIGH loop
    if XV(I) = '0' then
      XV(I) := '1';
      exit;
    else XV(I) := '0';
    end if;
   end loop;
   return XV;
  end INC;
end FINC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.finc.all;
entity SM_COUNT is
  port(CLK,CON,RESET: in std_logic;
       COUNT: inout std_logic_vector(3 downto 0));
end SM_COUNT;

architecture ALG of SM_COUNT is
  begin 
  process(CLK,CON,RESET)
    begin
      if RESET = '1' then
	COUNT <= "0000";
      elsif CLK'EVENT and CLK='1' then
	if CON = '1' then
       		COUNT <= INC(COUNT);
	end if;
      end if;
  end process;
end ALG;  
--Figure 9. 31 VHDL Description of a Counter Circuit

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ADD is
 port(CLK,RESET: in std_logic;A: in signed(1 downto 0); C: 
buffer signed(1 downto 0));
end ADD;

architecture ALG of ADD is
begin
process(CLK)
 begin
if RESET = '1' then C <= "00"; 
elsif CLK'EVENT and CLK = '1' then
    C  <= A + C;
end if;
 end process;
end ALG;
--Figure 9. 37 VHDL Description for Registered Adder

Library IEEE;
use IEEE.std_logic_1164.all;
entity TB_COUNT is
end;
 architecture TESTBENCH of TB_COUNT is
	signal CLK,CON,RESET : std_logic := '0';
	signal COUNT: std_logic_vector(3 downto 0);
	component SM_COUNT 
  		port(CLK,CON,RESET: in std_logic;
       		COUNT: inout std_logic_vector(3 downto 0));
	end component;
begin
 	UUT :SM_COUNT 
		Port Map (
			CLK,
			CON,
			RESET,     
			COUNT	);
	SignalSource : process
	begin
         CON <= '0', '1' after 60 ns;
         RESET <= '1', '0' after 40 ns;
         CLK <= '1', '0' after 50 ns, '1' after 100 ns,
         '0' after 150 ns,'1' after 200 ns,
         '0' after 250 ns, '1' after 300 ns,
         '0' after 350 ns, '1' after 400 ns,
         '0' after 450 ns, '1' after 500 ns,
         '0' after 550 ns,	'1' after 600 ns,
         '0' after 650 ns, '1' after 700 ns,
         '0' after 750 ns, '1' after 800 ns,
         '0' after 850 ns, '1' after 900 ns,
         '0' after 950 ns, '1' after 1000 ns,
         '0' after 1050 ns, '1' after 1100 ns,
         '0' after 1150 ns,'1' after 1200 ns,
         '0' after 1250 ns, '1' after 1300 ns,
         '0' after 1350 ns, '1' after 1400 ns,
         '0' after 1450 ns, '1' after 1500 ns,
         '0' after 1550 ns, '1' after 1600 ns,
         '0' after 1650 ns, '1' after 1700 ns,
         '0' after 1750 ns, '1' after 1800 ns,
         '0' after 1850 ns, '1' after 1900 ns,
         '0' after 1950 ns, '1' after 2000 ns,
         '0' after 2050 ns, '1' after 2100 ns,
         '0' after 2150 ns;
		wait;
	end process;
	
end TESTBENCH;

  configuration CFG_TB_COUNT of TB_COUNT is
        for TESTBENCH
                for UUT : SM_COUNT 
                end for;
        end for;
   end;

--Figure 9. 46 Counter Test Bench 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TIME_TEST is
Port( A,B,C,EN,CLK,RESET: in STD_LOGIC; F: out STD_LOGIC);
end TIME_TEST;

architecture ALG of TIME_TEST is 
   signal  FF1,FF2: STD_LOGIC; 
  begin
      P1:process(RESET,CLK)
       begin
         if RESET = '1' then
           FF1 <=  '0';
        elsif ( CLK'EVENT and CLK = '1')
          FF1 <= A and B;
       end if;
     end process;
  P2: process(RESET,CLK)
          begin
         if RESET = '1' then
           FF2<=  '0';
        elsif ( CLK'EVENT and CLK = '1')
          FF2 <= FF1 and C;
       end if;
     end process;
       F <= FF2 and FF1 when EN = '1' else
                  'Z' when others;
     end ALG;
--Figure 9.50 Example Model (TIMECKT.VHD)