chapter5_models.vhd

James Armstrong VHDL Design , source code

entity PAR_TO_SER is
  port(LD,SHCLK: in BIT; PARIN: in BIT_VECTOR(0 to 7);
       BUSY: inout BIT := '0'; SO: out BIT);
end PAR_TO_SER;

architecture TWO_PROC of PAR_TO_SER is
  signal SH_COMP: BIT :='0';
  signal PREG: BIT_VECTOR(0 to 7);
begin
  LOAD:process(LD,SH_COMP)
  begin
    ---- Activities:
    if LD'EVENT and LD='1'and BUSY='0' then
      ----1)Register Load
      PREG <=  PARIN;
      ----2)Busy Set
      BUSY <= '1';
    end if;
      if SH_COMP'EVENT and SH_COMP='1' then
        ----3)Busy Reset
        BUSY <= '0';
      end if;
  end process LOAD;
  SHIFT:process(BUSY,SHCLK)
    variable COUNT: INTEGER;
    variable OREG: BIT_VECTOR(0 to 7);
  begin
    ----Activities:
    if BUSY'EVENT and BUSY = '1' then
      ----1)Shift Initialize
      COUNT := 7;
        OREG := PREG;
      SH_COMP <= '0';
    end if;
    if SHCLK'EVENT and SHCLK= '1'and BUSY='1' then
      ----2)Shift
      SO<=OREG(COUNT);
      COUNT := COUNT - 1;
      ----3)Shift Complete
      if COUNT < 0 then
        SH_COMP <= '1';
      end if;
    end if;
  end process SHIFT;
end TWO_PROC;
---Parallel to Serial Converter

entity BUFF_REG is
     generic(STRB_DEL,EN_DEL,ODEL: TIME);
     port(DI:  in BIT_VECTOR(1 to 8);
       STRB: in BIT;DS1:  in BIT;
       NDS2: in BIT;
       DO: out BIT_VECTOR(1 to 8));
  end BUFF_REG;
  --
  architecture THREE_PROC of BUFF_REG is
     signal REG: BIT_VECTOR(1 to 8);
     signal ENBLD: BIT;
  begin
  PREG: process(STRB)
     begin
        if (STRB = '1') then
           REG <=DI after STRB_DEL;
        end if;
  end process PREG;
  --
  ENABLE: process(DS1,NDS2)
     begin
        ENBLD <= DS1 and  not NDS2 after EN_DEL;
  end process ENABLE;
  --
  OUTPUT: process(REG,ENBLD)
     begin
        if (ENBLD = '1')
        then
           DO <= REG after ODEL;
        else
           DO <= "11111111" after ODEL;
        end if;
  end process OUTPUT;
  end THREE_PROC;
--Figure 5.9 Algorithmic VHDL description for buffered register.

architecture DATA_FLOW of BUFF_REG is
begin
  B:block(STRB = '1'and not STRB'STABLE)
    signal REG: BIT_VECTOR(1 to 8);
    signal ENBLD: BIT;
  begin
    REG <= guarded DI after STRB_DEL;       ---process REG
    ENBLD <= DS1 and not NDS2 after EN_DEL; ---proc ENABLE
    DO <=REG after ODEL when ENBLD = '1'    ---proc OUTPUT
         else "11111111" after ODEL;
  end block B;
end DATA_FLOW;
---Alternate architecture of the buffered register

entity BUFF_REG is
  generic(STRB_DEL,EN_DEL,ODEL,SUT,HT,MPW: TIME);
  port(DI:  in BIT_VECTOR(1 to 8);
       STRB: in BIT;DS1:  in BIT;
       NDS2: in BIT;
       DO: out BIT_VECTOR(1 to 8));
begin
  assert STRB'STABLE or (STRB = '0') or DI'STABLE(SUT)
    report  "Setup Time Failure";
  assert STRB'DELAYED(HT)'STABLE
         or (STRB'DELAYED(HT) = '0')
         or DI'STABLE(HT)
  report "Hold Time Failure";
  assert STRB'STABLE or (STRB = '1')
         or STRB'DELAYED'STABLE(MPW)
    report "Minimum pulse width failure";
end BUFF_REG;
--Buffered Register entity with timing checks

entity CLOCK_GENERATOR is
   generic (PER: TIME);
   port(RUN: in BIT;CLK: out BIT);
end CLOCK_GENERATOR;
--
architecture FEEDBACK of CLOCK_GENERATOR is
   signal CLOCK: BIT;
begin
  process (RUN,CLOCK)
    variable CLKE: BIT := '0';
  begin
    if RUN'EVENT then
      if RUN = '1' then
        CLKE := '1';
        CLOCK <= transport '0' after PER/2;
        CLOCK <= transport '1' after PER;
      else
        CLKE := '0';
      end if;
    end if;
    if(CLOCK'EVENT and CLOCK = '1' and CLKE = '1' ) then
      CLOCK <= transport '0' after PER/2;
      CLOCK <= transport '1' after PER;
    end if;
    CLK <= CLOCK;
  end process;
end FEEDBACK;
--Figure 5.14 Algorithmic description of clock generator

entity CONTROLLED_CTR is
  generic(SUT,MPW,ENCDEL,ENITDEL,RENITDEL,CLRDEL,
          CNTDEL,LIMDEL,COMPDEL: TIME);
  port(CLK,STRB: in BIT;
       CON:  in BIT_VECTOR(0 to 1);
       DATA:  in BIT_VECTOR(0 to 3);
       COUT: out BIT_VECTOR(0 to 3));
begin
  assert STRB'STABLE or STRB = '1' or DATA'STABLE(SUT)
    report "Set up time failure on DATA input"
    severity NOTE;
  assert STRB'STABLE or STRB = '0' or CON'STABLE(SUT)
    report "Set up time failure on CON input"
    severity NOTE;
 assert STRB'STABLE or STRB = '1' or STRB'DELAYED'STABLE(MPW)
    report "Pulse width failure on STRB"
    severity NOTE;
end CONTROLLED_CTR;
use work.counter_pac.all;
architecture PROCESS_IMPL of CONTROLLED_CTR is
  signal ENIT,RENIT: BIT;
  signal EN: BIT;
  signal CONSIG,LIM: BIT_VECTOR(0 to 3);
  signal CNT: BIT_VECTOR(0 to 3);
begin
  --
DECODE:process(STRB,RENIT)
  variable CONREG: BIT_VECTOR(0 to 1) := "00";
 begin
  if (STRB = '1') then
    CONREG := CON;
    case CONREG is
    -- Signal CLEAR is CONSIG(0).
      when "00" => CONSIG <= "1000" after ENCDEL;
    -- Signal LOAD is CONSIG(1).
      when "01" => CONSIG <= "0100" after ENCDEL;
    -- Signal CNTUP is CONSIG(2).
      when "10" => CONSIG <= "0010" after ENCDEL;
                   ENIT <= '1' after ENITDEL;
    -- Signal CNTDOWN is CONSIG(3).
      when "11" => CONSIG <= "0001" after ENCDEL;
                   ENIT <= '1' after ENITDEL;
    end case;
  end if;
  if RENIT'EVENT and RENIT = '1' then
     ENIT <= '0' after ENITDEL;
  end if;
 end process DECODE;
-- Code is continued on the next page.
--Figure 5.15 Algorithmic description of controlled counter in behavioral domain.

-- Continuation of controlled counter description.
LOAD_LIMIT:process(STRB)
 begin
  if(CONSIG(1)='1' and STRB'EVENT and STRB ='0') then
    LIM <= DATA after LIMDEL;
  end if;
 end process LOAD_LIMIT;
--
CTR: process(CONSIG(0),EN,CLK)
   variable CNTE: BIT:= '0';
 begin
  if (CONSIG(0)='1' and CONSIG(0)'EVENT) then
    CNT <= "0000" after CLRDEL;
  end if;
  if EN'EVENT then
    if EN = '1' then
      CNTE := '1';
    else
      CNTE := '0';
    end if;
  end if;
  if (CLK'EVENT and CLK =  '1' and CNTE = '1') then
    if (CONSIG(2)='1') then
      CNT <= INC(CNT);
    elsif (CONSIG(3)='1') then
      CNT <= DEC(CNT);
    end if;
  end if;
 end process CTR;
--
LIMIT_CHK: process(CNT,ENIT)
 begin
  if ENIT'EVENT then
    if ENIT = '1' then
      EN <= '1' after COMPDEL;
      RENIT <= '1' after RENITDEL;
    else
      RENIT <= '0' after RENITDEL;
    end if;
  elsif ((EN = '1') and (CNT = LIM)) then
    EN <= '0' after COMPDEL;
  end if;
 end process LIMIT_CHK;
COUT <= CNT;
end PROCESS_IMPL;
--Figure 5.16  Algorithmic description of controlled counter in behavioral domain.

use work.all;
entity COUNT_SYS is
  port(STRT,STROBE: in BIT;
       CON: in BIT_VECTOR(0 to 1);
       DATA_BUS: in BIT_VECTOR(0 to 3);
       CNT: out BIT_VECTOR(0 to 3));
end COUNT_SYS;
--
architecture TWO_COMPONENT of COUNT_SYS is
  signal CLK: BIT;
  component CLOCK_GEN
    generic(PER: TIME);
    port (RUN: in BIT; CLK: out BIT);
  end component;
  component CON_CTR
    generic(SUT,MPW,ENCDEL,ENITDEL,RENITDEL,
            CLRDEL,CNTDEL,LIMDEL,COMPDEL:TIME);
    port (CLK,STRB: in BIT;
          CON: in BIT_VECTOR(0 to 1);
          DATA: in BIT_VECTOR(0 to 3);
          COUT: out BIT_VECTOR(0 to 3));
  end component;
  for CLKGEN: CLOCK_GEN use entity CLOCK_GENERATOR(FEEDBACK);
  for CTR: CON_CTR use entity CONTROLLED_CTR (PROCESS_IMPL);
begin
  CLKGEN: CLOCK_GEN
    generic map(100 ns)
    port map(STRT,CLK);
  CTR: CON_CTR
    generic map(20 ns, 30 ns, 25 ns, 11 ns, 11 ns, 10 ns,
                15 ns,12 ns,10 ns)
    port map(CLK,STROBE,CON,DATA_BUS,CNT);
end TWO_COMPONENT;
--Figure 5.17 Structural architecture body of counter system.

use work.SYSTEM_4.all;
entity BUFF_REG is
  generic(STRB_DEL,DAV_DEL,ODEL: TIME);
  port(DI:  in MVL4_VECTOR(7 downto 0);
       STRB,EN: in MVL4;
       DAV: out MVL4;
       DO: out BUS1(7 downto 0):="ZZZZZZZZ");
end BUFF_REG;
--
architecture TWO_PROC of BUFF_REG is
  signal REG: MVL4_VECTOR(7 downto 0);
begin
  FRONT_END: process(STRB,EN)
  begin
    if STRB'EVENT and STRB = '1' then
      REG <=DI after STRB_DEL;
      DAV <= '1' after DAV_DEL;
    end if;
    if EN'EVENT and EN='1' then
      DAV <= '0' after DAV_DEL;
    end if;
  end process FRONT_END;
  --
  OUTPUT: process(REG,EN)
  begin
    if (EN = '1') then
      DO <= DRIVE(REG) after ODEL; else
      DO <= "ZZZZZZZZ" after ODEL;
    end if;
  end process OUTPUT;
end TWO_PROC;
--Figure 5.21 Buffered register model.

use work.SYSTEM_4.all;
--
entity RAM is
  generic(RDEL,DISDEL,ACK_DEL,ACK_PW: TIME);
   port(DATA: inout BUS1(7 downto 0):="ZZZZZZZZ";
        ADDR: in MVL4_VECTOR(4 downto 0);
        RD,WRITE,CS: in MVL4;
        RACK,WACK: out MVL4);
end RAM;
--
architecture SIMPLE of RAM   is
begin
 MEM: process (CS,RD,WRITE)
  type MEMORY is array(0 to 31) of MVL4_VECTOR(7 downto 0);
  variable MEM: MEMORY:= (others => (others  => '0'));
 begin
   if CS = '1' then
     if RD = '1' then
       DATA <= DRIVE(MEM(INTVAL(ADDR))) after RDEL;
       RACK <= '1' after ACK_DEL,
               '0' after ACK_DEL + ACK_PW;
     elsif WRITE = '1' then
       MEM (INTVAL(ADDR)):= SENSE(DATA,'1');
       WACK <= '1' after ACK_DEL, '0' after ACK_DEL+ACK_PW;
     end if;
   else
     DATA <= "ZZZZZZZZ"  after DISDEL;