chapter8_models.vhd

James Armstrong VHDL Design , source code

-- Device to compare two binary inputs.
--
entity COM is
  generic (D:time);
  port (N1, N0, M1, M0: in BIT;
        GE, LE, E, G, L: out BIT);
end COM;
--Figure 8.2 Entity specification for device COM.
-- Standard model for truth table using ARRAY structure.
-- This model can be directly translated into a ROM
-- implementation.
package TRUTH4x5 is
  constant NUM_OUTPUTS: INTEGER:=5;
  constant NUM_INPUTS: INTEGER:=4;
  constant NUM_ROWS: INTEGER:= 2 ** NUM_INPUTS;
  type WORD is array(NUM_OUTPUTS-1 downto 0) of BIT;
  type ADDR is array(NUM_INPUTS-1 downto 0) of BIT;
  type MEM is array (0 to NUM_ROWS-1) of WORD;
  constant TRUTH: MEM :=
                ("11100", "01001", "01001", "01001",
                 "10010", "11100", "01001", "01001",
                 "10010", "10010", "11100", "01001",
                 "10010", "10010", "10010", "11100");
  function INTVAL(VAL:ADDR) return INTEGER;
end TRUTH4x5;
package body TRUTH4x5 is
  function INTVAL(VAL: ADDR) return INTEGER is
    variable SUM: INTEGER:=0;
  begin
    for N in VAL'LOW to VAL'HIGH loop
      if VAL(N) = '1' then
        SUM := SUM + (2 ** N);
      end if;
    end loop;
    return SUM;
  end INTVAL;
end TRUTH4x5;
--  Description of COM using table lookup.
use work.TRUTH4x5.all;
architecture TABLE of COM is
begin
  process (N1,N0,M1,M0)
    variable INDEX: INTEGER;
    variable WOUT: WORD;
  begin
    INDEX := INTVAL (N1&N0&M1&M0);
    WOUT := TRUTH (INDEX);
    GE <= WOUT(4) after D;
    LE <= WOUT(3) after D;
    E  <= WOUT(2) after D;
    G  <= WOUT(1) after D;
    L  <= WOUT(0) after D;
  end process;
end TABLE;
--Figure 8.4 VHDL model for device COM using the ARRAY method.

Standard model for combinational logic,using a CASE
-- statement. This model can be directly translated
-- into a MUX implementation.
architecture MUX of COM is
begin
  process(N1,N0,M1,M0)
  begin
    case N1&N0&M1&M0 is
      when "0000" => GE <= '1' after D; LE <= '1' after D;
        E <= '1' after D; G <= '0' after D; L <= '0' after D;
      when "0001" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "0010" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "0011" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "0100" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "0101" => GE <= '1' after D; LE <= '1' after D;
        E <= '1' after D; G <= '0' after D; L <= '0' after D;
      when "0110" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "0111" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "1000" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "1001" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "1010" => GE <= '1' after D; LE <= '1' after D;
        E <= '1' after D; G <= '0' after D; L <= '0' after D;
      when "1011" => GE <= '0' after D; LE <= '1' after D;
        E <= '0' after D; G <= '0' after D; L <= '1' after D;
      when "1100" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "1101" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "1110" => GE <= '1' after D; LE <= '0' after D;
        E <= '0' after D; G <= '1' after D; L <= '0' after D;
      when "1111" => GE <= '1' after D; LE <= '1' after D;
        E <= '1' after D; G <= '0' after D; L <= '0' after D;
    end case;
  end process;
end MUX;
--Figure 8.6 VHDL model for device COM using the CASE method.

-- Improved CASE description. This model directly
-- corresponds to an 8x1 MUX implementation.
architecture MUX3 of COM is
begin
 process (N1, N0, M1, M0)
 begin
  case N1&N0&M1 is
   when "000" => GE <= not M0 after D; LE <= '1' after D;
    E <= not M0 after D; G <= '0' after D; L <= M0 after D;
   when "001" => GE <= '0' after D; LE <= '1' after D;
    E <= '0' after D; G <= '0' after D; L <= '1' after D;
   when "010" => GE <= '1' after D; LE <= M0 after D;
    E <= M0 after D; G <= not M0 after D; L <= '0' after D;
   when "011" => GE <= '0' after D; LE <= '1' after D;
    E <= '0' after D; G <= '0' after D; L <= '1' after D;
   when "100" => GE <= '1' after D; LE <= '0' after D;
    E <= '0' after D; G <= '1' after D; L <= '0' after D;
   when "101" => GE <= not M0 after D; LE <= '1' after D;
    E <= not M0 after D; G <= '0' after D; L <= M0 after D;
   when "110" => GE <= '1' after D; LE <= '0' after D;
    E <= '0' after D; G <= '1' after D; L <= '0' after D;
   when "111" => GE <= '1' after D; LE <= M0 after D;
    E <= M0 after D; G <= not M0 after D; L <= '0' after D;
  end case;
 end process;
end MUX3;
--Figure 8.8 An improved CASE style description for device COM.

-- Device to compare two binary inputs.
--
entity COM is
  generic (D:time);
  port (N1, N0, M1, M0: in BIT;
        GE, LE, E, G, L: out BIT);
end COM;
--
-- Optimum two-level product of sums data flow model.
--
architecture POSDF of COM is
  signal Z1,Z0: BIT;
begin
  Z1 <= (not N0 or M1 or M0) and (not N1 or M1) and
        (not N1 or not N0 or M0);
  Z0 <= (N1 or N0 or not M0) and (N1 or not M1) and
        (N0 or not M1 or not M0);
  LE <= Z1 after D;
  GE <= Z0 after D;
   E <= Z1 and Z0 after D;
   G <= Z0 and not Z1 after D;
   L <= Z1 and not Z0 after D;
end POSDF;
--Figure 8.12 VHDL description of data flow model for device COM.

-- Device to compare two binary inputs.
--
entity COM is
  generic (D:time);
  port (N1, N0, M1, M0: in BIT;
        GE, LE, E, G, L: out BIT);
end COM;
--
-- Optimum two-level product of sums data flow model.
-- Converted to two-level-nor data flow model.
--
architecture NORDF of COM is
begin
  process (N1, N0, M1, M0)
    variable Z1,Z0: BIT;
  begin
    Z1 := not(not(not N0 or M1 or M0) or not(not N1 or M1)
         or not(not N1 or not N0 or M0));
    Z0 := not(not(N1 or N0 or not M0) or not(N1 or not M1)
          or not(N0 or not M1 or not M0));
    LE <= Z1 after D;
    GE <= Z0 after D;
    E  <= not(not Z1 or not Z0) after D;
    G  <= not(not Z0 or Z1) after D;
    L  <= not(not Z1 or Z0) after D;
  end process;
end NORDF;
---Figure 8.13 Another VHDL description of a data flow model for device COM.

use work.all;
-- Device to compare two binary inputs.
entity COM is
  port (N1, N0, M1, M0: in BIT;
        GE, LE, E, G, L: out BIT);
end COM;
-- Two level OR-AND implementation derived from POS data
-- flow model
architecture TWO_LEVEL_OR_AND of COM is
  signal Z10,Z11,Z12,Z00,Z01,Z02: BIT;
  signal N0BAR,N1BAR,M0BAR,M1BAR: BIT;
  signal Z0,Z1,Z0NOT,Z1NOT: BIT;
  component NOT2G
    generic (D: TIME);
    port (I: in BIT; O: out BIT);
  end component;
  for all: NOT2G use entity NOT2(BEHAVIOR);
  component AND2G
    generic (D: TIME);
    port (I1, I2: in BIT; O: out BIT);
  end component;
  for all: AND2G use entity AND2(BEHAVIOR);
  component AND3G
    generic (D: TIME);
    port(I1,I2,I3: in BIT; O: out BIT);
  end component;
  for all: AND3G use entity AND3(BEHAVIOR);
  component OR2G
    generic (D: TIME);
    port(I1,I2: in BIT; O: out BIT);
  end component;
  for all: OR2G use entity OR2(BEHAVIOR);
  component OR3G
    generic (D: TIME);
    port (I1,I2,I3: in BIT; O: out BIT);
  end component;
  for all: OR3G use entity OR3(BEHAVIOR);
  component WIREG
    port (I: in BIT; O: out BIT);
    end component;
  for all: WIREG use entity WIRE(BEHAVIOR);
begin
---Figure 8.15a VHDL structural model for COM using two level OR-AND form.
C1: NOT2G
     generic map (2 ns)
     port map (N0, N0BAR);
 C2: NOT2G
     generic map (2 ns)
     port map (N1, N1BAR);
 C3: NOT2G
     generic map (2 ns)
     port map (M0, M0BAR);
 C4: NOT2G
     generic map (2 ns)
     port map (M1, M1BAR);
 C5: OR3G
     generic map (2 ns)
     port map (N0BAR, M1, M0, Z10);
 C6: OR2G
     generic map (2 ns)
     port map (N1BAR, M1, Z11);
 C7: OR3G
     generic map (2 ns)
     port map (N1BAR, N0BAR, M0, Z12);
 C8: AND3G
     generic map (2 ns)
     port map (Z10, Z11, Z12, Z1);
 C9: OR3G
     generic map (2 ns)
     port map (N1, N0, M0BAR, Z00);
 C10:OR2G
     generic map (2 ns)
     port map (N1, M1BAR, Z01);
 C11:OR3G
     generic map (2 ns)
     port map (N0, M1BAR, M0BAR, Z02);
 C12:AND3G
     generic map (2 ns)
     port map (Z00, Z01, Z02, Z0);
 C13:NOT2G
     generic map (2 ns)
     port map (Z1, Z1NOT);
 C14:NOT2G
     generic map (2 ns)
     port map (Z0, Z0NOT);
 C15:AND2G
     generic map (2 ns)
     port map (Z0, Z1, E);
 C16:AND2G
     generic map (2 ns)
     port map (Z0, Z1NOT, G);
 C17:AND2G
     generic map (2 ns)
     port map (Z1, Z0NOT, L);
 C18:WIREG
     port map (Z0, GE);
C19: WIREG
     port map (Z1, LE);
end TWO_LEVEL_OR_AND;
--Figure 8.15b VHDL structural model for COM using two level OR-AND form (cont.).

entity NOT2 is
  generic (D: TIME);
  port(I: in BIT; O: out BIT);
end NOT2;
--
architecture  BEHAVIOR of NOT2 is
begin
  O <= not I after D;
end BEHAVIOR;
--
entity AND2 is
  generic (D: TIME);
  port (I1,I2: in BIT; O: out BIT);
end AND2;
--
architecture BEHAVIOR of AND2 is
begin
  O <= I1 and I2 after D;
end BEHAVIOR;
--
entity AND3 is
  generic (D: TIME);
  port(I1,I2,I3: in BIT; O: out BIT);
end AND3;
--
architecture BEHAVIOR of AND3 is
begin
  O <= I1 and I2 and I3 after D;
end BEHAVIOR;
--
entity OR2 is
  generic (D: TIME);
  port(I1,I2: in BIT; O: out BIT);
end OR2;
--
architecture BEHAVIOR of OR2 is
begin
  O <= I1 or I2 after D;
end BEHAVIOR;
--
entity OR3 is
  generic (D: TIME);
  port (I1,I2,I3: in BIT; O: out BIT);
end OR3;
--
architecture BEHAVIOR of OR3 is
begin
  O <= I1 or I2 or I3 after D;
end BEHAVIOR;
--Figure 8.16a Specification of gate entities.
entity NOR2 is
  generic (D: TIME);
  port (I1,I2: in BIT; O: out BIT);
end NOR2;
--
architecture BEHAVIOR of NOR2 is
begin
  O <= I1 nor I2 after D;
end BEHAVIOR;
--
entity NOR3 is
  generic (D: TIME);
  port(I1,I2,I3: in BIT; O: out BIT);
end NOR3;
--
architecture BEHAVIOR of NOR3 is
begin
  O <= (I1 or I2) nor I3 after D;
end BEHAVIOR;
--
entity WIRE is
  port (I: in BIT; O: out BIT);
end WIRE;
--
architecture BEHAVIOR of WIRE is
begin
  O <= I;
end BEHAVIOR;
--Figure 8.16b?Specification of gate entities (cont.).

-- Serial to Parallel Converter
entity STOP is
  port (R, A, D, CLK: in BIT;
        Z: out BIT_VECTOR(3 downto 0);
        DONE: out BIT);
end STOP;

-- State Machine Description
-- for Serial to Parallel Converter (STOP)
architecture FSM_RTL of STOP is
  type STATE_TYPE is (S0, S1, S2, S3, S4, S5);
  signal STATE: STATE_TYPE;
  signal SHIFT_REG: BIT_VECTOR (3 downto 0);
begin
-- Process to update state at end of each clock period.
STATE: process (CLK)
  begin
    if CLK='1' then
      case STATE is
        when S0 =>
          -- Data Section
          -- Control Section
            if R='1' or A='0' then
              STATE <= S0;
            elsif R='0' and A='1' then
              STATE <= S1;
            end if;
        when S1 =>
          -- Data Section
          -- Shift in the first bit
            SHIFT_REG <= D & SHIFT_REG(3 downto 1);
          -- Control Section
            if R='0' then
              STATE <= S2;
            elsif R='1' then
              STATE <= S0;
            end if;
        when S2 =>
          -- Data Section
          -- Shift in the second bit
            SHIFT_REG <= D & SHIFT_REG(3 downto 1);
          -- Control Section
             if R='0' then
               STATE <= S3;
             elsif R='1' then
               STATE <= S0;
             end if;
--Figure 8.25a VHDL model for serial to parallel converter.
-- Continuation of architecture FSM_RTL of STOP
--
        when S3 =>
          -- Data Section
          -- Shift in the third bit
            SHIFT_REG <= D & SHIFT_REG(3 downto 1);
          -- Control Section
            if R='0' then
              STATE <= S4;
            elsif R='1' then
              STATE <= S0;
            end if;
        when S4 =>
          -- Data Section