chapter4_models.vhd

James Armstrong VHDL Design , source code

entity STATEMENTS is
  port(X,Y,Z: in INTEGER; -- Note that entity ports are
       B: out INTEGER);   -- always signals.
end STATEMENTS;

architecture  PROP_DELAY of STATEMENTS is
  signal AS: INTEGER;
begin
 process (X,Y,Z)
 begin
   AS <= X*Y after 2 ns;   --Statement (1)
   B  <= AS+Z after 2 ns;  --Statement (2)
 end process;
end PROP_DEL;

architecture INSTANTANEOUS of STATEMENTS is
begin
 process(X,Y,Z)
   variable AV,BV: INTEGER;
 begin
   AV := X*Y;  --Statement (3)
   BV := AV+Z; --Statement (4)
   B <= BV;
 end process;
end INSTANTANEOUS;
--Figure 4.2	Complete code for instantaneous and delayed assignment statements.

entity STATEMENTS is
  port(X,Y,Z: in INTEGER; -- Note: entity ports are
       BS: out INTEGER);  -- always signals.
end STATEMENTS;

architecture CONCURRENT of STATEMENTS is
  signal AS: INTEGER;
begin
  AS <= X*Y;   --Statement S1
  BS <= AS+Z;  --Statement S2
end PROP_DEL;

architecture SEQUENTIAL of STATEMENTS is
begin
 process(X,Y,Z)
   variable AV,BV: INTEGER;
 begin
   AV := X*Y;  --Statement S3
   BV := AV+Z; --Statement S4
   BS <= BV;
 end process;
end SEQUENTIAL;
--Figure 4.6	VHDL code to illustrate concurrent and sequential statements.

entity BUFF is
  port(X: in BIT; Z: out BIT);
end BUFF;

architecture  ONE of BUFF is
begin
  process(X)
    variable Y1: BIT;
  begin
    Y1 := X;
    Z <= Y1 after 1 ns;
  end process;
end ONE;

architecture TWO of BUFF is
  signal Y2: BIT;
begin
  Y2 <= X ;
  Z <= Y2 ;
end TWO;

architecture THREE of BUFF is
  signal Y3: BIT;
begin
  Y3 <= X;
  Z <= Y3 after 1 ns;
end THREE;

architecture FOUR of BUFF is
  signal Y4: BIT;
begin
  Y4 <= X after 1 ns;
  Z <= Y4 after 1 ns;
end FOUR;
--Figure 4.8	Four different delay situations.

architecture FIVE of BUFF is
  signal Y5: BIT;
begin
  process(X)
  begin
    Y5 <= X;
    Z  <= Y5;
  end process;
end FIVE;
architecture FIVE_A of BUFF is
  signal Y5: BIT;
begin
  process(X,Y5)
  begin
    Y5 <= X;
    Z  <= Y5;
  end process;
end FIVE_A;
--Figure 4.10	Effect of delta delay.

entity MAJ3 is
  generic(DEL: TIME);
  port(X: in BIT_VECTOR(0 to 2); Z: out BIT);
end MAJ3;

architecture DATAFLOW of MAJ3 is
begin
  Z <= (X(0) and X(1)) or (X(1) and X(2))
    or (X(0) and X(2)) after DEL;
end DATAFLOW;
      -- (a) VHDL description

-- Figure 4.16 A majority/consensus element.

entity AND2 is
  generic(DEL: TIME);
  port(I1,I2: in BIT; O: out BIT);
end AND2;
architecture DF of AND2 is
begin
  O <= I1 and I2 after DEL;
end DF;
--Figure 4.18 AND gate primitive.

entity BUF is
  generic(DATA_DEL,Z_DEL: TIME);
  port(I,EN: in BIT; O: out BIT);
end BUF;
architecture ALG of BUF is
begin
  process(I,EN)
  begin
    if EN = '1' then
      O <= I after DATA_DEL;
    else
      O <=  '1' after Z_DEL;
    end if;
  end process;
end ALG;
--Figure 4.19   Buffer primitive.

entity FULL_ADDER is
  generic(SUM_DEL,CARRY_DEL:TIME);
  port(A,B,CI: in BIT; SUM,COUT: out BIT);
end FULL_ADDER;

architecture DF of FULL_ADDER is
begin
  SUM <= A xor B xor CI after SUM_DEL;
  COUT <= (A and B) or (A and CI) or (B and CI)
          after CARRY_DEL;
end DF;
--Figure 4.20 Full adder primitive.

entity FOUR_TO_1_MUX is
  generic(DEL: TIME);
  port(IN0,IN1,IN2,IN3: in BIT_VECTOR(3 downto 0);
       SEL: in BIT_VECTOR(1 downto 0);
       O: out BIT_VECTOR(3 downto 0));
end FOUR_TO_1_MUX;

architecture DF of FOUR_TO_1_MUX is
begin
  O <= IN0 after DEL when SEL = "00" else
       IN1 after DEL when SEL = "01" else
       IN2 after DEL when SEL = "10" else
       IN3 after DEL;
end DF;
--Figure 4.22 Multiplexer primitive.

entity TWO_TO_4_DEC is
  generic(DEL: TIME);
  port(I: in  BIT_VECTOR(1 downto 0);
       O: out BIT_VECTOR(3 downto 0));
end TWO_TO_4_DEC;

architecture ALG of TWO_TO_4_DEC is
begin
  process(I)
  begin
    case I is
      when "00" => O<= "0001" after DEL;
      when "01" => O<= "0010" after DEL;
      when "10" => O<= "0100" after DEL;
      when "11" => O<= "1000" after DEL;
    end case;
  end process;
end ALG;
--Figure 4.23 Decoder primitive.

entity FOUR_TO_2_ENC is
  generic(DEL: TIME);
  port(I: in  BIT_VECTOR(3 downto 0);
       O: out BIT_VECTOR(1 downto 0));
  end FOUR_TO_2_ENC;

architecture DF of FOUR_TO_2_ENC is
begin
  O <= "00" after DEL when I(0) = '1' else
       "01" after DEL when I(1) = '1' else
       "10" after DEL when I(2) = '1' else
       "11" after DEL;
end DF;
--Figure 4.24 Encoder primitive.

entity SHIFTER is
  generic(DEL: TIME);
  port(DATA_IN: in BIT_VECTOR(3 downto 0);
       SR,SL: in BIT; IL,IR: in BIT;
       DATA_OUT: out BIT_VECTOR(3 downto 0));
end SHIFTER;

architecture  ALG of SHIFTER is
begin
  process(SR,SL,DATA_IN,IL,IR)
    variable CON: BIT_VECTOR(0 to 1);
  begin
    CON := SR&SL;
    case CON is
      when "00" => DATA_OUT <= DATA_IN after DEL;
      when "01" => DATA_OUT <= DATA_IN(2 downto 0) & IL
                   after DEL;
      when "10" => DATA_OUT <= IR & DATA_IN(3 downto 1)
                   after DEL;
      when "11" => DATA_OUT <= DATA_IN after DEL;
    end case;
  end process;
end ALG;
--Figure 4.25 Shifter primitive.

package PRIMS is
  procedure ADD(A,B: in BIT_VECTOR; CIN: in BIT;
                SUM: out BIT_VECTOR; COUT: out BIT);
  function INC(X : BIT_VECTOR) return BIT_VECTOR;
  function DEC(X : BIT_VECTOR) return BIT_VECTOR;
  function INTVAL(VAL : BIT_VECTOR) return INTEGER;
end PRIMS;
package body PRIMS is
  procedure ADD(A,B: in BIT_VECTOR; CIN: in BIT;
                SUM: out BIT_VECTOR; COUT: out BIT) is
    variable SUMV,AV,BV: BIT_VECTOR(A'LENGTH-1 downto 0);
    variable CARRY: BIT;
  begin
    AV := A;
    BV := B;
    CARRY := CIN;
    for I in 0 to SUMV'HIGH loop
      SUMV(I) := AV(I) xor BV(I) xor CARRY;
      CARRY := (AV(I) and BV(I)) or (AV(I) and CARRY)
                or (BV(i) and CARRY);
    end loop;
    COUT := CARRY;
    SUM := SUMV;
  end ADD;

  function INC(X : BIT_VECTOR) return BIT_VECTOR is
    variable XV: BIT_VECTOR(X'LENGTH-1 downto 0);
  begin
    XV := X;
    for I in 0 to XV'HIGH loop
      if XV(I) = '0' then
        XV(I) := '1';
        exit;
      else XV(I) := '0';
      end if;
    end loop;
    return XV;
  end INC;
--Figure 4.26 Data operations package.

function DEC(X : BIT_VECTOR) return BIT_VECTOR is
    variable XV: BIT_VECTOR(X'LENGTH-1 downto 0);
  begin
    XV := X;
    for I in 0 to XV'HIGH loop
      if XV(I) = '1' then
        XV(I) := '0';
        exit;
      else XV(I) := '1';
      end if;
    end loop;
    return XV;
  end DEC;

  function INTVAL ( VAL: BIT_VECTOR) return INTEGER is
    variable VALV: BIT_VECTOR(VAL'LENGTH - 1 downto 0);
    variable SUM: INTEGER := 0;
  begin
    VALV := VAL;
    for N in VALV'LOW to VALV'HIGH loop
      if VALV(N) = '1' then
        SUM := SUM + (2**N);
      end if;
    end loop;
    return SUM;
  end INTVAL;
end PRIMS;
-- Figure 4.26 (continued)Data operations package

use work.PRIMS.all;
entity ALU is
  generic(DEL: TIME);
  port(A,B: in BIT_VECTOR(3 downto 0); CI: in BIT;
       FSEL: in BIT_VECTOR(1 downto 0);
       F: out BIT_VECTOR(3 downto 0); COUT: out BIT);
end ALU;
architecture ALG of ALU is
begin
  process(A,B,CI,FSEL)
    variable  FV: BIT_VECTOR(3 downto 0);
    variable COUTV: BIT;
  begin
    case FSEL is
      when "00" => F <= A after DEL;
      when "01" => F <= not(A) after DEL;
      when "10" => ADD(A,B,CI,FV,COUTV);
                   F <= FV after DEL;
                   COUT <= COUTV after DEL;
      when "11" => F <= A and B after DEL;
    end case;
  end process;
end ALG;
--Figure 4.27 ALU primitive.

entity PLA is
  generic(AND_DEL,OR_DEL: TIME);
  port(X: in BIT_VECTOR(1 to 3);
       Z: out BIT_VECTOR(1 to 4));
end PLA;
architecture CONNECTION_MATRIX of PLA is
  signal R: BIT_VECTOR(1 to 4);
begin
 AND_PLANE: process(X)
   variable RV: BIT_VECTOR(1 to 4);
   type AND_ARRAY is array( 1 to 4, 1 to 3, 1 to 2 ) of BIT;
   variable AND_PL: AND_ARRAY :=
     ((('0','1'),('0','0'),('0','0')),
      (('0','0'),('1','0'),('1','0')),
      (('1','0'),('1','0'),('0','1')),
      (('1','0'),('0','1'),('1','0')));
 begin
   for I in 1 to 4 loop
     RV(I) := '0';
     for J in 1 to 3 loop
     assert not(AND_PL(I,J,1) = '1' and AND_PL(I,J,2) = '1')
       report "Error in AND plane wiring";
       if AND_PL(I,J,1) = '1' then
         RV(I) := RV(I) or X(J);
       end if;
       if AND_PL(I,J,2) = '1' then RV(I) := RV(I) or not X(J);
       end if;
     end loop;
     R(I) <= not RV(I) after AND_DEL;
   end loop;
 end process AND_PLANE;
 OR_PLANE: process(R)
   variable ZV: BIT_VECTOR(1 to 4);