代码搜索：Behaviour
找到约 1,042 项符合「Behaviour」的源代码
代码结果 1,042
www.eeworm.com/read/461590/7223938
vhd adder_unsigned.vhd
use work.dp32_types.all;
entity adder_unsigned is
generic(width : positive);
port(a,b : in bit_vector(width-1 downto 0);
y : out bit_vector(width-1 downto 0);
o : out bit );
end
www.eeworm.com/read/461590/7223951
vhd mux8.vhd
use work.dp32_types.all;
entity mux8 is
generic (width : positive;
Tpd : Time := unit_delay);
port (i0, i1, i2, i3, i4, i5, i6, i7 : in bit_vector(width-1 downto 0);
y : out bi
www.eeworm.com/read/461590/7223952
vhd mux4.vhd
use work.dp32_types.all;
entity mux4 is
generic (width : positive;
Tpd : Time := unit_delay);
port (i0, i1, i2, i3: in bit_vector(width-1 downto 0);
y : out bit_vector(width-1
www.eeworm.com/read/461590/7223957
vhd subtractor_signed.vhd
use work.dp32_types.all;
entity subtractor_signed is
generic (width : positive);
port(a,b : in bit_vector(width-1 downto 0);
y : out bit_vector(width-1 downto 0);
n,z : out bit);
e
www.eeworm.com/read/461590/7223924
vhd xor.vhd
use work.dp32_types.all;
entity g_xor is
generic(width : positive);
port(a,b : in bit_vector(width-1 downto 0);
y : out bit_vector(width-1 downto 0));
end g_xor;
architecture beh
www.eeworm.com/read/453446/7420461
vhd vhdl code1.vhd
-- This is the VHDL code for the counter example from _The VHDL
-- Cookbook_ by Peter Ashenden. The propogation delay has been removed.
entity count2 is
port (clock : in bit; q1, q0 : out bit)
www.eeworm.com/read/453446/7420462
bak vhdl code1.bak
-- This is the VHDL code for the counter example from _The VHDL
-- Cookbook_ by Peter Ashenden. The propogation delay has been removed.
entity count2 is
port (clock : in bit; q1, q0 : out bit)
www.eeworm.com/read/461590/7223900
vhd latch_buffer_32.vhd
--
-- $RCSfile: latch_buffer_32.vhd,v $
-- $Revision: 1.1 $
-- $Author: petera $
-- $Date: 90/05/24 16:57:44 $
--
use work.dp32_types.all;
entity latch_buffer_32 is
generic (Tpd : Time := unit_del
www.eeworm.com/read/173924/9630078
txt 1(3).txt
Library IEEE;
Use IEEE.Std_Logic_1164.All;
Entity muxdecoder Is
Port(a:In std_Logic_Vector(3 downto 0);
b:In Std_Logic_Vector(3 downto 0);
clk:In Std_Logic;
y:out Std_Logic_Vector
www.eeworm.com/read/461590/7223923
vhd pc_reg.vhd
--
-- $RCSfile: PC_reg.vhd,v $
-- $Revision: 1.2 $
-- $Author: petera $
-- $Date: 90/05/29 10:13:02 $
--
use work.dp32_types.all;
entity PC_reg is
generic (Tpd : Time := unit_delay);
port (d : i